Trivedi; Vivek

Patent Applications and Registrations

Patent applications and USPTO patent grants for Trivedi; Vivek.The latest application filed is for "network device, system and method having a rotated chip floorplan".

Company Profile

1.11.7

Trivedi; Vivek - Fremont CA
Trivedi; Vivek - Elk Grove CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Configurable-aggregation retimer with media-dedicated controllers Grant 11,327,913 - Morrison , et al. May 10, 2	2022-05-10
Low-latency signaling-link retimer Grant 11,258,696 - Morrison , et al. February 22, 2	2022-02-22
Low-latency retimer with seamless clock switchover Grant 11,150,687 - Mohan , et al. October 19, 2	2021-10-19
Baseboard interconnection device, system and method Grant 10,198,389 - Motamedi , et al. Fe	2019-02-05
System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks Grant 9,443,053 - Jayakumar , et al. September 13, 2	2016-09-13
System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks Grant 9,390,209 - Jayakumar , et al. July 12, 2	2016-07-12
System for and method of tuning clock networks constructed using variable drive-strength clock inverters with variable drive-strength clock drivers built out of a smaller subset of base cells Grant 9,305,129 - Jayakumar , et al. April 5, 2	2016-04-05
Baseboard Interconnection Device, System And Method App 20160012006 - Motamedi; Amir H. ; et al.	2016-01-14
Network Device, System And Method Having A Rotated Chip Floorplan App 20160014885 - Motamedi; Amir H. ; et al.	2016-01-14
Integrated circuit optimization Grant 9,098,664 - Trivedi , et al. August 4, 2	2015-08-04
System For And Method Of Placing And Routing Clock Stations Using Variable Drive-strength Clock Drivers Built Out Of A Smaller Subset Of Base Cells For Hybrid Tree-mesh Clock Distribution Networks App 20150186589 - Jayakumar; Nikhil ; et al.	2015-07-02
System For And Method Of Combining Cmos Inverters Of Multiple Drive Strengths To Create Tune-able Clock Inverters Of Variable Drive Strengths In Hybrid Tree-mesh Clock Distribution Networks App 20150186560 - Jayakumar; Nikhil ; et al.	2015-07-02
System For And Method Of Tuning Clock Networks Constructed Using Variable Drive-strength Clock Inverters With Variable Drive-strength Clock Drivers Built Out Of A Smaller Subset Of Base Cells App 20150186583 - Jayakumar; Nikhil ; et al.	2015-07-02
Integrated Circuit Optimization App 20140181778 - Trivedi; Vivek ; et al.	2014-06-26
Integrated circuit optimization Grant 8,683,416 - Trivedi , et al. March 25, 2	2014-03-25
Timing analysis apparatus, systems, and methods Grant 7,299,433 - Clement , et al. November 20, 2	2007-11-20
Timing analysis apparatus, systems, and methods App 20040250224 - Clement, Manuel S. ; et al.	2004-12-09

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