Trivedi; Ritesh
Patent Applications and Registrations
Patent applications and USPTO patent grants for Trivedi; Ritesh.The latest application filed is for "load for non-volatile memory drain bias".
- Trivedi; Ritesh - Fair Oaks CA
- Trivedi, Ritesh - Orangevale CA
| Patent | Date |
|---|---|
| Kicker for non-volatile memory drain bias Grant 6,744,671 - Trivedi , et al. June 1, 2 | 2004-06-01 |
| Drain bias for non-volatile memory Grant 6,535,423 - Trivedi , et al. March 18, 2 | 2003-03-18 |
| Load for non-volatile memory drain bias App 20020126527 - Trivedi, Ritesh ; et al. | 2002-09-12 |
| Sample and hold voltage reference source Grant 6,434,049 - Trivedi , et al. August 13, 2 | 2002-08-13 |
| Method And Apparatus For Gating A Global Column Select Line With Address Transition Detection App 20020101766 - Baltar, Robert ; et al. | 2002-08-01 |
| Local sensing of non-volatile memory App 20020085424 - Trivedi, Ritesh ; et al. | 2002-07-04 |
| Drain bias for non-volatile memory App 20020085421 - Trivedi, Ritesh ; et al. | 2002-07-04 |
| Differential Signal Path For High Speed Data Transmission In Flash Memory App 20020085425 - Srinivasan, Balaji ; et al. | 2002-07-04 |
| Drain bias for non-volatile memory App 20020085422 - Trivedi, Ritesh ; et al. | 2002-07-04 |
| Sample And Hold Voltage Reference Source App 20020085413 - Trivedi, Ritesh ; et al. | 2002-07-04 |
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