Trivedi; Jigish D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Trivedi; Jigish D..The latest application filed is for "capacitorless dram on bulk silicon".

Company Profile

0.73.83

Trivedi; Jigish D. - Boise ID
Trivedi; Jigish D - Boise ID
Trivedi; Jigish D. - Bosise ID
Trivedi; Jigish D. - Bosie ID

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Capacitorless DRAM on bulk silicon Grant 8,971,086 - Mathew , et al. March 3, 2	2015-03-03
Capacitorless Dram On Bulk Silicon App 20130279277 - Mathew; Suraj ; et al.	2013-10-24
Recessed access device for a memory Grant 8,541,836 - Beigel , et al. September 24, 2	2013-09-24
Capacitorless DRAM on bulk silicon Grant 8,466,517 - Mathew , et al. June 18, 2	2013-06-18
Recessed Access Device for a Memory App 20130062678 - Beigel; Kurt D. ; et al.	2013-03-14
Recessed access device for a memory Grant 8,319,280 - Beigel , et al. November 27, 2	2012-11-27
Capacitorless Dram On Bulk Silicon App 20120199908 - Mathew; Suraj ; et al.	2012-08-09
Capacitorless DRAM on bulk silicon Grant 8,158,471 - Mathew , et al. April 17, 2	2012-04-17
Recessed Access Device for a Memory App 20120001245 - Beigel; Kurt D. ; et al.	2012-01-05
Methods of forming recessed access devices associated with semiconductor constructions Grant 8,067,286 - Parekh , et al. November 29, 2	2011-11-29
Recessed access device for a memory Grant 8,035,160 - Beigel , et al. October 11, 2	2011-10-11
Low resistance metal silicide local interconnects and a method of making Grant 8,003,526 - Trivedi August 23, 2	2011-08-23
Methods of Forming Recessed Access Devices Associated with Semiconductor Constructions App 20110117725 - Parekh; Kunal R. ; et al.	2011-05-19
Liner for shallow trench isolation Grant 7,919,829 - Trivedi , et al. April 5, 2	2011-04-05
Methods of forming recessed access devices associated with semiconductor constructions Grant 7,897,460 - Parekh , et al. March 1, 2	2011-03-01
Capacitorless Dram On Bulk Silicon App 20110020988 - MATHEW; SURAJ ; et al.	2011-01-27
Capacitorless DRAM on bulk silicon Grant 7,829,399 - Mathew , et al. November 9, 2	2010-11-09
Low Resistance Metal Silicide Local Interconnects And A Method Of Making App 20100167528 - Trivedi; Jigish D.	2010-07-01
Low resistance metal silicide local interconnects and a method of making Grant 7,701,059 - Trivedi April 20, 2	2010-04-20
Recessed Access Device For A Memory App 20100072532 - Beigel; Kurt D. ; et al.	2010-03-25
Sub-micron space liner and filler process Grant 7,659,181 - Smythe, III , et al. February 9, 2	2010-02-09
Recessed access device for a memory Grant 7,645,671 - Beigel , et al. January 12, 2	2010-01-12
Isolation trench Grant 7,622,769 - Smythe, III , et al. November 24, 2	2009-11-24
Capacitorless Dram On Bulk Silicon App 20090190394 - Mathew; Suraj ; et al.	2009-07-30
Capacitorless DRAM on bulk silicon Grant 7,538,389 - Mathew , et al. May 26, 2	2009-05-26
Capacitorless DRAM on bulk silicon Grant 7,517,744 - Mathew , et al. April 14, 2	2009-04-14
Methods for forming shallow trench isolation Grant 7,514,366 - Trivedi , et al. April 7, 2	2009-04-07
Methods of Forming Recessed Access Devices Associated With Semiconductor Constructions App 20080166856 - Parekh; Kunal R. ; et al.	2008-07-10
Methods of forming recessed access devices associated with semiconductor constructions Grant 7,384,849 - Parekh , et al. June 10, 2	2008-06-10
Recessed access device for a memory App 20080113478 - Beigel; Kurt D. ; et al.	2008-05-15
Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same Grant 7,332,388 - Trivedi , et al. February 19, 2	2008-02-19
Method of fabricating stacked local interconnect structure Grant 7,314,822 - Trivedi January 1, 2	2008-01-01
Liner For Shallow Trench Isolation App 20070290293 - Trivedi; Jigish D. ; et al.	2007-12-20
Edge intensive antifuse and method for making the same Grant 7,279,772 - Trivedi October 9, 2	2007-10-09
Liner for shallow trench isolation Grant 7,271,464 - Trivedi , et al. September 18, 2	2007-09-18
Method for making an edge intensive antifuse Grant 7,269,898 - Trivedi September 18, 2	2007-09-18
Edge intensive antifuse and method for making the same Grant 7,235,858 - Trivedi June 26, 2	2007-06-26
Method for forming an antifuse Grant 7,210,224 - Trivedi May 1, 2	2007-05-01
Sub-micron Space Liner And Filler Process App 20070059899 - Smythe; John A. III ; et al.	2007-03-15
Edge intensive antifuse Grant 7,189,634 - Trivedi March 13, 2	2007-03-13
Transistor gate and local interconnect Grant 7,176,096 - Trivedi February 13, 2	2007-02-13
Edge intensive antifuse and method for making the same App 20070029639 - Trivedi; Jigish D.	2007-02-08
Edge intensive antifuse and method for making the same App 20070022599 - Trivedi; Jigish D.	2007-02-01
Methods For Forming Shallow Trench Isolation App 20070004131 - Trivedi; Jigish D. ; et al.	2007-01-04
Method of forming a field effect transistor with halo implant regions Grant 7,153,731 - Abbott , et al. December 26, 2	2006-12-26
Capacitorless dram on bulk silicon App 20060284210 - Mathew; Suraj ; et al.	2006-12-21
Capacitorless DRAM on bulk silicon App 20060278926 - Mathew; Suraj ; et al.	2006-12-14
Isolation trench App 20060267131 - Smythe; John A. III ; et al.	2006-11-30
Methods of forming recessed access devices associated with semiconductor constructions App 20060216894 - Parekh; Kunal R. ; et al.	2006-09-28
Sub-micron space liner and densification process Grant 7,112,513 - Smythe, III , et al. September 26, 2	2006-09-26
Method of forming a field effect transistor Grant 7,112,482 - Abbott , et al. September 26, 2	2006-09-26
Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same App 20060205133 - Trivedi; Jigish D. ; et al.	2006-09-14
Method for forming a notched gate App 20060177983 - Trivedi; Jigish D.	2006-08-10
Method for forming a notched gate Grant 7,078,284 - Trivedi July 18, 2	2006-07-18
Edge intensive antifuse Grant 7,057,218 - Trivedi June 6, 2	2006-06-06
Dual depth trench isolation App 20060043522 - Trivedi; Jigish D.	2006-03-02
Liner for shallow trench isolation App 20060043521 - Trivedi; Jigish D. ; et al.	2006-03-02
Method to fabricate surface p-channel CMOS Grant 7,005,342 - Mathew , et al. February 28, 2	2006-02-28
Integrated transistor circuitry Grant 6,987,291 - Abbott , et al. January 17, 2	2006-01-17
Suppression of cross diffusion and gate depletion App 20050266666 - Trivedi, Jigish D. ; et al.	2005-12-01
Methods of forming refractory metal silicide components and methods of restricting silicon surface migration of a silicon structure Grant 6,953,749 - Hu , et al. October 11, 2	2005-10-11
Sub-micron space liner and densification process App 20050186755 - Smythe, John A. III ; et al.	2005-08-25
Stacked local interconnect structure and method of fabricating same App 20050130403 - Trivedi, Jigish D.	2005-06-16
Method of forming a dual damascene interconnect by selective metal deposition Grant 6,893,957 - Trivedi , et al. May 17, 2	2005-05-17
Method of fabricating a stacked local interconnect structure App 20050095848 - Trivedi, Jigish D.	2005-05-05
Dual depth trench isolation Grant 6,875,697 - Trivedi April 5, 2	2005-04-05
Methods of forming conductive contacts Grant 6,872,660 - Trivedi , et al. March 29, 2	2005-03-29
Stacked local interconnect structure and method of fabricating same Grant 6,858,525 - Trivedi February 22, 2	2005-02-22
Method to fabricate surface p-channel CMOS App 20050026357 - Mathew, Suraj J. ; et al.	2005-02-03
Dual Depth Trench Isolation App 20050020088 - Trivedi, Jigish D.	2005-01-27
Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same Grant 6,844,601 - Trivedi , et al. January 18, 2	2005-01-18
Method of forming a field effect transistor App 20050003627 - Abbott, Todd R. ; et al.	2005-01-06
Edge intensive antifuse and method for making the same App 20050001285 - Trivedi, Jigish D.	2005-01-06
Method of fabricating a stacked local interconnect structure Grant 6,831,001 - Trivedi December 14, 2	2004-12-14
Edge intensive antifuse and method for making the same App 20040238916 - Trivedi, Jigish D.	2004-12-02
Edge intensive antifuse and method for making the same App 20040238917 - Trivedi, Jigish D.	2004-12-02
Semiconductor constructions Grant 6,818,997 - Trivedi November 16, 2	2004-11-16
Method to fabricate surface p-channel CMOS Grant 6,809,014 - Mathew , et al. October 26, 2	2004-10-26
Sidewall strap for complementary semiconductor structures and method of making same Grant 6,806,134 - Trivedi , et al. October 19, 2	2004-10-19
Edge intensive antifuse and method for making the same App 20040188800 - Trivedi, Jigish D.	2004-09-30
Sacrificial deposition layer as screening material for implants into a wafer during the manufacture of a semiconductor device Grant 6,797,596 - Ahmed , et al. September 28, 2	2004-09-28
Dual depth trench isolation Grant 6,790,781 - Trivedi September 14, 2	2004-09-14
Sidewall strap for complementary semiconductor structures and method of making same Grant 6,770,921 - Trivedi , et al. August 3, 2	2004-08-03
Methods Of Forming Refractory Metal Silicide Components And Methods Of Restricting Silicon Surface Migration Of A Silicon Structure App 20040132286 - Hu, Yongjun ; et al.	2004-07-08
MOS transistors with nitrogen in the gate oxide of the p-channel transistor Grant 6,744,102 - Trivedi , et al. June 1, 2	2004-06-01
Methods of forming conductive contacts App 20040102036 - Trivedi, Jigish D. ; et al.	2004-05-27
Method for forming an antifuse Grant 6,740,575 - Trivedi May 25, 2	2004-05-25
Dual damascene interconnect Grant 6,724,089 - Trivedi , et al. April 20, 2	2004-04-20
Suppression of cross diffusion and gate depletion App 20040048431 - Trivedi, Jigish D. ; et al.	2004-03-11
Sacrificial deposition layer as screening material for implants into a wafer during the manufacture of a semiconductor device App 20040043586 - Ahmed, Fawad ; et al.	2004-03-04
Edge Intensive Antifuse Device Structure App 20040021199 - Trivedi, Jigish D.	2004-02-05
Edge intensive antifuse and method for making the same App 20040023441 - Trivedi, Jigish D.	2004-02-05
Edge intensive antifuse and method for making the same App 20040021200 - Trivedi, Jigish D.	2004-02-05
Edge intensive antifuse device structure Grant 6,683,365 - Trivedi January 27, 2	2004-01-27
Silicon plugs and local interconnect for embedded memory and system-on-chip (SOC) applications Grant 6,677,650 - Fischer , et al. January 13, 2	2004-01-13
Methods of forming conductive contacts Grant 6,673,715 - Trivedi , et al. January 6, 2	2004-01-06
Semiconductor structures Grant 6,670,681 - Trivedi December 30, 2	2003-12-30
Notched damascene planar poly/metal gate and methods thereof App 20030235943 - Trivedi, Jigish D.	2003-12-25
Stacked local interconnect structure and method of fabricating same App 20030211676 - Trivedi, Jigish D.	2003-11-13
Stacked local interconnect structure and method of fabricating same App 20030211675 - Trivedi, Jigish D.	2003-11-13
Dual depth trench isolation App 20030207525 - Trivedi, Jigish D.	2003-11-06
Conductive structure in an integrated circuit Grant 6,639,319 - Trivedi , et al. October 28, 2	2003-10-28
Transistor gate and local interconnect Grant 6,630,718 - Trivedi October 7, 2	2003-10-07
Cross-diffusion resistant dual-polycide semiconductor structure and method Grant 6,613,617 - Trivedi , et al. September 2, 2	2003-09-02
Process for forming low resistance metal silicide local interconnects Grant 6,605,533 - Trivedi August 12, 2	2003-08-12
Method of forming a field effect transistor Grant 6,599,789 - Abbott , et al. July 29, 2	2003-07-29
Methods of forming transistors and semiconductor processing methods of forming transistor gates Grant 6,599,805 - Trivedi July 29, 2	2003-07-29
Semiconductor processing methods, and semiconductor constructions App 20030137055 - Trivedi, Jigish D.	2003-07-24
Semiconductor structures App 20030132485 - Trivedi, Jigish D.	2003-07-17
Local interconnect structures and methods for making the same App 20030124845 - Trivedi, Jigish D.	2003-07-03
Dual damascene interconnect App 20030116858 - Trivedi, Jigish D. ; et al.	2003-06-26
Methods of forming conductive contacts App 20030077890 - Trivedi, Jigish D. ; et al.	2003-04-24
Semiconductor processing methods, and semiconductor constructions Grant 6,548,401 - Trivedi April 15, 2	2003-04-15
Semiconductor processing method of forming field effect transistors Grant 6,541,395 - Trivedi , et al. April 1, 2	2003-04-01
Cross-diffusion resistant dual-polycide semiconductor structure and method App 20030057453 - Trivedi, Jigish D. ; et al.	2003-03-27
Sidewall strap for complementary semiconductor structures and method of making same App 20030054614 - Trivedi, Jigish D. ; et al.	2003-03-20
Sidewall strap for complementary semiconductor structures and method of making same App 20030042514 - Trivedi, Jigish D. ; et al.	2003-03-06
Cross-diffusion Resistant Dual-polycide Semiconductor Structure And Method App 20030042628 - Trivedi, Jigish D. ; et al.	2003-03-06
Method for forming a notched damascene planar poly/metal gate Grant 6,524,901 - Trivedi February 25, 2	2003-02-25
Method of selectively forming local interconnects using design rules App 20030036258 - Abbott, Todd ; et al.	2003-02-20
Method of simultaneous formation of local interconnect and gate electrode App 20030036240 - Trivedi, Jigish D.	2003-02-20
Integrated circuitry App 20030015766 - Abbott, Todd R. ; et al.	2003-01-23
Method Of Forming A Field Effect Transistor App 20030008438 - Abbott, Todd R. ; et al.	2003-01-09
Semiconductor Cmos Structures With An Undoped Region App 20020190339 - Trivedi, Jigish D.	2002-12-19
Stacked local interconnect structure and method of fabricating same Grant 6,482,689 - Trivedi November 19, 2	2002-11-19
Method to reduce transistor channel length using SDOX App 20020130376 - Wang, Zhongze ; et al.	2002-09-19
Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications App 20020132467 - Fischer, Mark ; et al.	2002-09-19
Suppression of cross diffusion and gate depletion App 20020132441 - Trivedi, Jigish D. ; et al.	2002-09-19
Method to fabricate surface p-channel CMOS App 20020132412 - Mathew, Suraj J. ; et al.	2002-09-19
Method of selectively forming local interconnects using design rules App 20020114180 - Abbott, Todd ; et al.	2002-08-22
Local interconnect structures and methods for making the same Grant 6,436,805 - Trivedi August 20, 2	2002-08-20
Stacked local interconnect structure and method of fabricating same App 20020102836 - Trivedi, Jigish D.	2002-08-01
P-type FET in a CMOS with nitrogen atoms in the gate dielectric Grant 6,417,546 - Trivedi , et al. July 9, 2	2002-07-09
Integrated circuitry and semiconductor processing method of forming field effect transistors App 20020079542 - Trivedi, Jigish D. ; et al.	2002-06-27
Conductive structure in an integrated circuit App 20020068433 - Trivedi, Jigish D. ; et al.	2002-06-06
Stacked local interconnect structure and method of fabricating same App 20020068397 - Trivedi, Jigish D.	2002-06-06
Local interconnect structures and methods for making the same App 20020068429 - Trivedi, Jigish D.	2002-06-06
Methods of forming transistors and semiconductor processing methods of forming transistor gates App 20020064920 - Trivedi, Jigish D.	2002-05-30
Dual damascene interconnect App 20020061645 - Trivedi, Jigish D. ; et al.	2002-05-23
Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same App 20020055251 - Trivedi, Jigish D. ; et al.	2002-05-09
Stacked local interconnect structure and method of fabricating same App 20020055214 - Trivedi, Jigish D.	2002-05-09
Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same App 20020047205 - Trivedi, Jigish D. ; et al.	2002-04-25
Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications Grant 6,376,358 - Fischer , et al. April 23, 2	2002-04-23
Methods Of Forming Integrated Circuitry. App 20020019114 - Trivedi, Jigish D.	2002-02-14
Method For Fabricating Local Interconnect Structure For Integrated Circuit Devices, Source Structures App 20020009871 - TRIVEDI, JIGISH D. ; et al.	2002-01-24
Methods of forming transistors Grant 6,335,254 - Trivedi January 1, 2	2002-01-01
Methods of forming refractory metal silicide components and methods of restricting silicon surface migration of a silicon structure App 20010051427 - Hu, Yongjun ; et al.	2001-12-13
Local Interconnect Structure For Integrated Circuit Devices, Source Structure For The Same, And Method For Fabricating The Same App 20010045650 - TRIVEDI, JIGISH D.	2001-11-29
Use of non-ion-implanted resistive silicon oxynitride films as resistors App 20010045618 - Trivedi, Jigish D.	2001-11-29
P-type Fet In A Cmos With Nitrogen Atoms In The Gate Dielectric App 20010040256 - TRIVEDI, JIGISH D. ; et al.	2001-11-15
Process for forming low resistance metal silicide local interconnects App 20010026960 - Trivedi, Jigish D.	2001-10-04
Low resistance metal silicide local interconnects and a method of making Grant 6,294,464 - Trivedi September 25, 2	2001-09-25
Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same App 20010019159 - Trivedi, Jigish D.	2001-09-06
Integrated circuitry and semiconductor processing method of forming field effect transistors Grant 6,093,661 - Trivedi , et al. July 25, 2	2000-07-25
Local interconnect comprising titanium nitride barrier layer Grant 5,847,463 - Trivedi , et al. December 8, 1	1998-12-08

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