Trivedi; Anuj

Patent Applications and Registrations

Patent applications and USPTO patent grants for Trivedi; Anuj.The latest application filed is for "method and system for determining circuit failure rate".

Company Profile

2.8.7

Trivedi; Anuj - Dublin CA
Trivedi; Anuj - Santa Clara CA US
Trivedi; Anuj - Sunnyvale CA
Trivedi; Anuj - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and system for determining circuit failure rate Grant 10,599,808 - Saraswat , et al.	2020-03-24
Method and System for Determining Circuit Failure Rate App 20190258773 - Saraswat; Govind ; et al.	2019-08-22
Overlay display of data from different databases Grant 10,360,340 - Verma , et al.	2019-07-23
Method and system for determining circuit failure rate Grant 10,282,507 - Saraswat , et al.	2019-05-07
Hierarchical grid for spatial querying Grant 9,977,789 - Zhu , et al. May 22, 2	2018-05-22
Overlay Display Of Data From Different Databases App 20180096095 - Verma; Rupesh ; et al.	2018-04-05
Method And System For Determining Circuit Failure Rate App 20170147738 - Saraswat; Govind ; et al.	2017-05-25
Hierarchical Grid For Spatial Querying App 20130138682 - Zhu; Jay J. ; et al.	2013-05-30
Method of modeling circuit cells for powergrid analysis Grant 7,283,943 - Qi , et al. October 16, 2	2007-10-16
N-level down hierarchical powergrid analysis Grant 7,260,805 - Yan , et al. August 21, 2	2007-08-21
Electromigration risk analysis in integrated circuit power interconnect systems using pseudo dynamic simulation Grant 6,880,139 - Mau , et al. April 12, 2	2005-04-12
Electromigration risk analysis in integrated circuit power interconnect systems using pseudo dynamic simulation App 20040168136 - Mau, Hendrik T. ; et al.	2004-08-26
Self adjusting linear MOSFET simulation techniques App 20040049370 - Stanley, Douglas R. ; et al.	2004-03-11

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