Trickett; Douglas M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Trickett; Douglas M..The latest application filed is for "chamferless via structures".

Company Profile

1.17.14

Trickett; Douglas M. - Altamont NY
Trickett; Douglas M - Altamont NY US
Trickett; Douglas M - Boise ID
Trickett; Douglas M. - Boise ID
Trickett, Douglas M. - Kudamatsu-shi JP
Trickett; Douglas M. - Kudamatsu JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Chamferless via structures Grant 10,957,588 - Lenhardt , et al. March 23, 2	2021-03-23
Chamferless via structures Grant 10,937,694 - Lenhardt , et al. March 2, 2	2021-03-02
Chamferless via structures Grant 10,903,118 - Lenhardt , et al. January 26, 2	2021-01-26
Chamferless Via Structures App 20190333813 - LENHARDT; Mark L. ; et al.	2019-10-31
Chamferless Via Structures App 20190333814 - LENHARDT; Mark L. ; et al.	2019-10-31
Chamferless via structures Grant 10,388,565 - Lenhardt , et al. A	2019-08-20
Chamferless Via Structures App 20180269103 - LENHARDT; Mark L. ; et al.	2018-09-20
Chamferless via structures Grant 10,032,668 - Lenhardt , et al. July 24, 2	2018-07-24
Methods employing sacrificial barrier layer for protection of vias during trench formation Grant 9,799,559 - Siddiqui , et al. October 24, 2	2017-10-24
Self aligned via in integrated circuit Grant 9,768,113 - Feurprier , et al. September 19, 2	2017-09-19
Chamferless Via Structures App 20170133268 - LENHARDT; Mark L. ; et al.	2017-05-11
Chamferless via structures Grant 9,613,862 - Lenhardt , et al. April 4, 2	2017-04-04
Chamferless Via Structures App 20170062275 - LENHARDT; Mark L. ; et al.	2017-03-02
Chamferless Via Structures App 20170062331 - LENHARDT; Mark L. ; et al.	2017-03-02
Self Aligned Via In Integrated Circuit App 20160379929 - Feurprier; Yannick ; et al.	2016-12-29
Self aligned via in integrated circuit Grant 9,385,078 - Feurprier , et al. July 5, 2	2016-07-05
Self aligned via in integrated circuit Grant 9,373,582 - Feurprier , et al. June 21, 2	2016-06-21
Forming interconnect features with reduced sidewall tapering Grant 9,373,543 - Mont , et al. June 21, 2	2016-06-21
Method for top oxide rounding with protection of patterned features Grant 9,252,051 - Lee , et al. February 2, 2	2016-02-02
Method for thinning a bonding wafer Grant 8,476,165 - Trickett , et al. July 2, 2	2013-07-02
Method to remove capping layer of insulation dielectric in interconnect structures Grant 8,202,803 - Feurprier , et al. June 19, 2	2012-06-19
Ultra-low-k dual damascene structure and method of fabricating App 20120064713 - RUSSELL; Noel ; et al.	2012-03-15
Method to remove capping layer of insulation dielectric in interconnect structures App 20110143542 - FEURPRIER; Yannick ; et al.	2011-06-16
Method For Thinning A Bonding Wafer App 20100255682 - Trickett; Douglas M. ; et al.	2010-10-07
Damage-free ashing process and system for post low-k etch Grant 7,279,427 - Nishino , et al. October 9, 2	2007-10-09
Damage-free ashing process and system for post low-k etch App 20070032087 - Nishino; Masaru ; et al.	2007-02-08
Method for coating internal surface of plasma processing chamber App 20050112289 - Trickett, Douglas M. ; et al.	2005-05-26
Method for coating internal surface of plasma processing chamber App 20050084617 - Trickett, Douglas M. ; et al.	2005-04-21
Method for coating internal surface of plasma processing chamber Grant 6,875,477 - Trickett , et al. April 5, 2	2005-04-05
Method for coating internal surface of plasma processing chamber App 20040151841 - Trickett, Douglas M. ; et al.	2004-08-05

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.