Travis; Edward O.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Travis; Edward O..The latest application filed is for "apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures".

Company Profile

0.80.67

Travis; Edward O. - Austin TX
Travis; Edward O - Austin TX US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures Grant 10,014,257 - Reber , et al. July 3, 2	2018-07-03
Fuse/resistor utilizing interconnect and vias and method of making Grant 9,685,405 - Shroff , et al. June 20, 2	2017-06-20
Integrated circuit design using pre-marked circuit element object library Grant 9,652,577 - Travis , et al. May 16, 2	2017-05-16
Apparatus And Method For Placing Stressors Within An Integrated Circuit Device To Manage Electromigration Failures App 20170069572 - Reber; Douglas M. ; et al.	2017-03-09
3D device packaging using through-substrate posts Grant 9,515,006 - Reber , et al. December 6, 2	2016-12-06
3D device packaging using through-substrate pillars Grant 9,508,701 - Reber , et al. November 29, 2	2016-11-29
3D device packaging using through-substrate posts Grant 9,508,702 - Reber , et al. November 29, 2	2016-11-29
Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures Grant 9,455,220 - Shroff , et al. September 27, 2	2016-09-27
Teleconferencing environment having auditory and visual cues Grant 9,445,050 - Travis , et al. September 13, 2	2016-09-13
Capping layer interface interruption for stress migration mitigation Grant 9,443,804 - Shroff , et al. September 13, 2	2016-09-13
Teleconferencing Environment Having Auditory And Visual Cues App 20160142674 - TRAVIS; Edward O. ; et al.	2016-05-19
Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit Grant 9,318,409 - Reber , et al. April 19, 2	2016-04-19
Integrated Circuit Design Using Pre-Marked Circuit Element Object Library App 20160098510 - Travis; Edward O. ; et al.	2016-04-07
Integrated Circuit Heater For Reducing Stress In The Integrated Circuit Material And Chip Leads Of The Integrated Circit, And For Optimizing Performance Of Devices Of The Integrated Circuit App 20160093549 - Reber; Douglas M. ; et al.	2016-03-31
Semiconductor device with embedded heat spreading Grant 9,245,817 - Travis , et al. January 26, 2	2016-01-26
Thin beam deposited fuse Grant 9,236,344 - Reber , et al. January 12, 2	2016-01-12
Apparatus And Method For Placing Stressors Within An Integrated Circuit Device To Manage Electromigration Failures App 20150348898 - Shroff; Mehul D. ; et al.	2015-12-03
Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device Grant 9,142,507 - Shroff , et al. September 22, 2	2015-09-22
Stress Migration Mitigation Utilizing Induced Stress Effects In Metal Trace Of Integrated Circuit Device App 20150249048 - Shroff; Mehul D. ; et al.	2015-09-03
Stress migration mitigation Grant 9,122,829 - Reber , et al. September 1, 2	2015-09-01
Semiconductor device with vias on a bridge connecting two buses Grant 9,122,812 - Reber , et al. September 1, 2	2015-09-01
Method for forming an electrical connection between metal layers Grant 9,082,824 - Reber , et al. July 14, 2	2015-07-14
Semiconductor Manufacturing Using Design Verification With Markers App 20150178438 - DEMIRCAN; ERTUGRUL ; et al.	2015-06-25
Electronic device including a capacitor and a process of forming the same Grant 9,064,785 - Smith , et al. June 23, 2	2015-06-23
Thin Beam Deposited Fuse App 20150137311 - Reber; Douglas M. ; et al.	2015-05-21
Method for forming an electrical connection between metal layers Grant 9,032,615 - Travis , et al. May 19, 2	2015-05-19
3d Device Packaging Using Through-substrate Posts App 20150091187 - Reber; Douglas M. ; et al.	2015-04-02
3d Device Packaging Using Through-substrate Pillars App 20150091178 - Reber; Douglas M. ; et al.	2015-04-02
Method for forming an electrical connection between metal layers Grant 8,972,922 - Reber , et al. March 3, 2	2015-03-03
Capping Layer Interface Interruption for Stress Migration Mitigation App 20150035151 - Shroff; Mehul D. ; et al.	2015-02-05
Stress Migration Mitigation App 20150040092 - Reber; Douglas M. ; et al.	2015-02-05
Method for forming an integrated circuit having a programmable fuse Grant 8,946,000 - Reber , et al. February 3, 2	2015-02-03
Method of protecting against via failure and structure therefor Grant 8,941,242 - Shroff , et al. January 27, 2	2015-01-27
Fuse/resistor Utilizing Interconnect And Vias And Method Of Making App 20140353797 - SHROFF; Mehul D. ; et al.	2014-12-04
Method For Forming An Electrical Connection Between Metal Layers App 20140353841 - Reber; Douglas M. ; et al.	2014-12-04
Semiconductor Device With Embedded Heat Spreading App 20140329383 - TRAVIS; EDWARD O. ; et al.	2014-11-06
Mismatch verification device and methods thereof Grant 8,856,705 - Shroff , et al. October 7, 2	2014-10-07
Semiconductor Device With Vias On A Bridge Connecting Two Buses App 20140258582 - REBER; DOUGLAS M. ; et al.	2014-09-11
Multi-layer process-induced damage tracking and remediation Grant 8,832,624 - Shroff , et al. September 9, 2	2014-09-09
Thin Beam Deposited Fuse App 20140239440 - Reber; Douglas M. ; et al.	2014-08-28
Semiconductor device with embedded heat spreading Grant 8,796,841 - Travis , et al. August 5, 2	2014-08-05
Integrated assist features for epitaxial growth Grant 8,741,743 - Zia , et al. June 3, 2	2014-06-03
Semiconductor device with vias on a bridge connecting two buses Grant 8,736,071 - Reber , et al. May 27, 2	2014-05-27
Integrated assist features for epitaxial growth Grant 8,722,519 - Zia , et al. May 13, 2	2014-05-13
Method and system for derived layer checking for semiconductor device design Grant 8,707,231 - Reber , et al. April 22, 2	2014-04-22
Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules Grant 8,694,926 - Reber , et al. April 8, 2	2014-04-08
Method For Forming An Electrical Connection Between Metal Layers App 20140094029 - REBER; DOUGLAS M. ; et al.	2014-04-03
Method For Forming An Electrical Connection Between Metal Layers App 20140038317 - Travis; Edward O. ; et al.	2014-02-06
Method And System For Derived Layer Checking For Semiconductor Device Design App 20140040839 - Reber; Douglas M. ; et al.	2014-02-06
Method For Forming An Electrical Connection Between Metal Layers App 20140038319 - Reber; Douglas M. ; et al.	2014-02-06
Method for forming an electrical connection between metal layers Grant 8,640,072 - Reber , et al. January 28, 2	2014-01-28
Techniques For Checking Computer-aided Design Layers Of A Device To Reduce The Occurrence Of Missing Deck Rules App 20130326446 - Reber; Douglas M. ; et al.	2013-12-05
Device matching tool and methods thereof Grant 8,601,430 - Shroff , et al. December 3, 2	2013-12-03
Via placement and electronic circuit design processing method and electronic circuit design utilizing same Grant 8,595,667 - Shroff , et al. November 26, 2	2013-11-26
Mismatch Verification Device And Methods Thereof App 20130305202 - Shroff; Mehul ; et al.	2013-11-14
Semiconductor device with heat dissipation Grant 8,581,390 - Travis , et al. November 12, 2	2013-11-12
Semiconductor Device With Embedded Heat Spreading App 20130264700 - TRAVIS; EDWARD O. ; et al.	2013-10-10
Semiconductor Device With Heat Dissipation App 20130264698 - Travis; Edward O. ; et al.	2013-10-10
Method Of Protecting Against Via Failure And Structure Therefor App 20130147051 - SHROFF; MEHUL D. ; et al.	2013-06-13
Semiconductor Device With Vias On A Bridge Connecting Two Buses App 20130105986 - REBER; DOUGLAS M. ; et al.	2013-05-02
Integrated Assist Features for Epitaxial Growth App 20110269300 - Zia; Omar ; et al.	2011-11-03
Integrated assist features for epitaxial growth Grant 8,003,539 - Zia , et al. August 23, 2	2011-08-23
Method and apparatus for indicating directionality in integrated circuit manufacturing Grant 7,858,487 - Travis , et al. December 28, 2	2010-12-28
Method And Apparatus For Indicating Directionality In Integrated Circuit Manufacturing App 20100112779 - TRAVIS; EDWARD O. ; et al.	2010-05-06
Method and apparatus for indicating directionality in integrated circuit manufacturing Grant 7,635,920 - Travis , et al. December 22, 2	2009-12-22
EPI T-gate structure for CoSi.sub.2 extendibility Grant 7,622,339 - Hall , et al. November 24, 2	2009-11-24
Integrated assist features for epitaxial growth bulk tiles with compensation Grant 7,565,639 - Zia , et al. July 21, 2	2009-07-21
Spacer T-gate structure for CoSi.sub.2 extendibility Grant 7,510,922 - Hall , et al. March 31, 2	2009-03-31
Electronic Device Including A Capacitor And A Process Of Forming The Same App 20090020849 - Smith; Bradley P. ; et al.	2009-01-22
Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation Grant 7,470,624 - Zia , et al. December 30, 2	2008-12-30
Integrated assist features for epitaxial growth App 20080166859 - Zia; Omar ; et al.	2008-07-10
Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation App 20080168418 - Zia; Omar ; et al.	2008-07-10
Integrated assist features for epitaxial growth bulk tiles with compensation App 20080168417 - Zia; Omar ; et al.	2008-07-10
Integrated assist features for epitaxial growth App 20080164559 - Zia; Omar ; et al.	2008-07-10
Primitive cell method for front end physical design Grant 7,386,821 - Higman , et al. June 10, 2	2008-06-10
Method of implementing polishing uniformity and modifying layout data Grant 7,322,014 - Travis , et al. January 22, 2	2008-01-22
Primitive Cell Method For Front End Physical Design App 20080005717 - Higman; Jack M. ; et al.	2008-01-03
Die level metal density gradient for improved flip chip package reliability Grant 7,276,435 - Pozder , et al. October 2, 2	2007-10-02
Method and apparatus for indicating directionality in integrated circuit manufacturing App 20070194392 - Travis; Edward O. ; et al.	2007-08-23
EPI T-gate structure for CoSi2 extendibility App 20070173004 - Hall; Mark D. ; et al.	2007-07-26
Spacer T-gate structure for CoSi2 extendibility App 20070173002 - Hall; Mark D. ; et al.	2007-07-26
Integrated circuit having structural support for a flip-chip interconnect pad and method therefor Grant 7,247,552 - Pozder , et al. July 24, 2	2007-07-24
Semiconductor device for reducing photovolatic current Grant 7,238,579 - Smith , et al. July 3, 2	2007-07-03
Method Of Implementing Polishing Uniformity And Modifying Layout Data App 20070061768 - Travis; Edward O. ; et al.	2007-03-15
Method of implementing polishing uniformity and modifying layout data Grant 7,146,593 - Travis , et al. December 5, 2	2006-12-05
Integrated circuit having structural support for a flip-chip interconnect pad and method therefor App 20060154470 - Pozder; Scott K. ; et al.	2006-07-13
Semiconductor device for reducing photovolatic current Grant 6,956,281 - Smith , et al. October 18, 2	2005-10-18
Method of implementing polishing uniformity and modifying layout data App 20050097490 - Travis, Edward O. ; et al.	2005-05-05
Semiconductor device for reducing photovolatic current App 20050093110 - Smith, Bradley P. ; et al.	2005-05-05
Method for providing a dummy feature and structure thereof Grant 6,764,919 - Yu , et al. July 20, 2	2004-07-20
Method For Providing A Dummy Feature And Structure Thereof App 20040121577 - Yu, Kathleen C. ; et al.	2004-06-24
Semiconductor device for reducing photovolatic current App 20040036150 - Smith, Bradley P. ; et al.	2004-02-26
Semiconductor device and process for generating an etch pattern Grant 6,613,688 - Brown , et al. September 2, 2	2003-09-02
Semiconductor tiling structure and method of formation Grant 6,614,062 - Chheda , et al. September 2, 2	2003-09-02
Method of forming an integrated circuit device using dummy features and structure thereof Grant 6,611,045 - Travis , et al. August 26, 2	2003-08-26
Method for adding features to a design layout and process for designing a mask Grant 6,593,226 - Travis , et al. July 15, 2	2003-07-15
Method of forming an integrated circuit device using dummy features and structure thereof App 20020179902 - Travis, Edward O. ; et al.	2002-12-05
Selective sizing of features to compensate for resist thickness variations in semiconductor devices Grant 6,489,083 - Smith , et al. December 3, 2	2002-12-03
Semiconductor device, a process for a semiconductor device, and a process for making a masking database Grant 6,459,156 - Travis , et al. October 1, 2	2002-10-01
Semiconductor tiling structure and method of formation App 20020093071 - Chheda, Sejal N. ; et al.	2002-07-18
Method for adding features to a design layout and process for designing a mask App 20020050655 - Travis, Edward O. ; et al.	2002-05-02
Semiconductor device having a bond pad Grant 5,814,893 - Hsu , et al. September 29, 1	1998-09-29
Process for forming a semiconductor device having a bond pad Grant 5,661,082 - Hsu , et al. August 26, 1	1997-08-26

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