| Patent | Date |
|---|
Space efficient checkpoint facility and technique for processor with integrally indexed register mapping and free-list arrays
Grant 9,672,044 - Tran June 6, 2 | 2017-06-06 |
Systems and methods for reconfiguring cache memory
Grant 9,547,593 - Tran January 17, 2 | 2017-01-17 |
Apparatus and method for memory copy at a processor
Grant 9,524,162 - Tran , et al. December 20, 2 | 2016-12-20 |
Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
Grant 9,424,190 - Tran August 23, 2 | 2016-08-23 |
Method and apparatus for dynamic resource partition in simultaneous multi-thread microprocessor
Grant 9,417,920 - Tran August 16, 2 | 2016-08-16 |
Register renaming scheme with checkpoint repair in a processing device
Grant 9,170,818 - Tran October 27, 2 | 2015-10-27 |
Data processing system with latency tolerance execution
Grant 9,135,014 - Tran , et al. September 15, 2 | 2015-09-15 |
Systems and methods for handling instructions of in-order and out-of-order execution queues
Grant 9,110,656 - Tran , et al. August 18, 2 | 2015-08-18 |
Systems and methods for reducing branch misprediction penalty
Grant 9,092,225 - Tran , et al. July 28, 2 | 2015-07-28 |
Microprocessor systems and methods for a combined register file and checkpoint repair register
Grant 9,063,747 - Tran June 23, 2 | 2015-06-23 |
Method and Apparatus for Dynamic Resource Partition in Simultaneous Multi-Thread Microprocessor
App 20150100965 - Tran; Thang M. | 2015-04-09 |
Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance
Grant 8,984,254 - Tran , et al. March 17, 2 | 2015-03-17 |
Microprocessor systems and methods for latency tolerance execution
Grant 8,972,700 - Tran March 3, 2 | 2015-03-03 |
Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
Grant 8,966,232 - Tran February 24, 2 | 2015-02-24 |
Systems and methods for handling instructions of in-order and out-of-order execution queues
Grant 8,966,229 - Tran , et al. February 24, 2 | 2015-02-24 |
Techniques for reducing processor power consumption through dynamic processor resource allocation
Grant 8,959,371 - Tran February 17, 2 | 2015-02-17 |
Microprocessor systems and methods for handling instructions with multiple dependencies
Grant 8,904,150 - Tran , et al. December 2, 2 | 2014-12-02 |
Techniques for Utilizing Transaction Lookaside Buffer Entry Numbers to Improve Processor Performance
App 20140095784 - Tran; Thang M. ; et al. | 2014-04-03 |
Space Efficient Checkpoint Facility And Technique For Processor With Integrally Indexed Register Mapping And Free-list Arrays
App 20140040595 - Tran; Thang M. | 2014-02-06 |
Systems and methods for configuring load/store execution units
Grant 8,639,884 - Tran January 28, 2 | 2014-01-28 |
Techniques For Reducing Processor Power Consumption Through Dynamic Processor Resource Allocation
App 20140025967 - Tran; Thang M. | 2014-01-23 |
Apparatus And Method For Dynamic Allocation Of Execution Queues
App 20130297912 - Tran; Thang M. ; et al. | 2013-11-07 |
Apparatus And Method For Memory Copy At A Processor
App 20130290639 - Tran; Thang M. ; et al. | 2013-10-31 |
Data Processing System Operable In Single And Multi-thread Modes And Having Multiple Caches And Method Of Operation
App 20130212585 - Tran; Thang M. | 2013-08-15 |
Data Processing System With Latency Tolerance Execution
App 20130212358 - Tran; Thang M. ; et al. | 2013-08-15 |
Systems And Methods For Reducing Branch Misprediction Penalty
App 20130198490 - Tran; Thang M. ; et al. | 2013-08-01 |
Branch target buffer addressing in a data processor
Grant 8,458,447 - Tran , et al. June 4, 2 | 2013-06-04 |
Data Processing System Operable In Single And Multi-thread Modes And Having Multiple Caches And Method Of Operation
App 20130046936 - Tran; Thang M. | 2013-02-21 |
Systems And Methods For Handling Instructions Of In-order And Out-of-order Execution Queues
App 20130046957 - TRAN; THANG M. ; et al. | 2013-02-21 |
Systems And Methods For Handling Instructions Of In-order And Out-of-order Execution Queues
App 20130046956 - TRAN; THANG M. ; et al. | 2013-02-21 |
Branch Target Buffer Addressing In A Data Processor
App 20120324209 - Tran; Thang M. ; et al. | 2012-12-20 |
Data Processing System With Latency Tolerance Execution
App 20120303936 - Tran; Thang M. ; et al. | 2012-11-29 |
Microprocessor Systems And Methods For Handling Instructions With Multiple Dependencies
App 20120303935 - TRAN; THANG M. ; et al. | 2012-11-29 |
Microprocessor Systems And Methods For Register File Checkpointing
App 20120278592 - TRAN; THANG M. | 2012-11-01 |
Apparatus And Method For Checkpoint Repair In A Processing Device
App 20120278596 - Tran; Thang M. | 2012-11-01 |
Microprocessor Systems And Methods For Latency Tolerance Execution
App 20120221835 - TRAN; THANG M. | 2012-08-30 |
Systems And Methods For Reconfiguring Cache Memory
App 20120221793 - TRAN; THANG M. | 2012-08-30 |
Systems And Methods For Configuring Load/store Execution Units
App 20120221796 - TRAN; THANG M. | 2012-08-30 |
Cache Tag Memory
App 20100169578 - NYCHKA; Robert ; et al. | 2010-07-01 |
Microprocessor with independent SIMD loop buffer
Grant 7,330,964 - Tran , et al. February 12, 2 | 2008-02-12 |
System and method for power efficient memory caching
Grant 7,330,936 - Tran , et al. February 12, 2 | 2008-02-12 |
Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays
Grant 7,266,676 - Tran , et al. September 4, 2 | 2007-09-04 |
Configurable cache system depending on instruction type
Grant 7,237,065 - Tran , et al. June 26, 2 | 2007-06-26 |
Loop detection and capture in the intstruction queue
App 20070113059 - Tran; Thang M. | 2007-05-17 |
Microprocessor with indepedent SIMD loop buffer
App 20070113058 - Tran; Thang M. ; et al. | 2007-05-17 |
Centralized resolution of conditional instructions
App 20070050610 - Tran; Thang M. ; et al. | 2007-03-01 |
Configurable cache system depending on instruction type
App 20060271738 - Tran; Thang M. ; et al. | 2006-11-30 |
Methods and apparatus for instruction alignment including current instruction pointer logic responsive to instruction length information
Grant 7,134,000 - Tran , et al. November 7, 2 | 2006-11-07 |
System and method for power efficent memory caching
App 20060047884 - Tran; Thang M. ; et al. | 2006-03-02 |
Memory system for supporting multiple parallel accesses at very high frequencies
Grant 6,963,962 - Ramagopal , et al. November 8, 2 | 2005-11-08 |
Methods and apparatus for setting up hardware loops in a deeply pipelined processor
App 20050102659 - Singh, Ravi Pratap ; et al. | 2005-05-12 |
Methods and apparatus for instruction alignment
App 20040236926 - Tran, Thang M. ; et al. | 2004-11-25 |
Method and apparatus for branch prediction based on branch targets
App 20040186985 - Tran, Thang M. ; et al. | 2004-09-23 |
Memory system for supporting multiple parallel accesses at very high frequencies
App 20030196058 - Ramagopal, Hebbalalu S. ; et al. | 2003-10-16 |
Data address prediction structure and a method for operating the same
Grant 6,604,190 - Tran August 5, 2 | 2003-08-05 |
Line-oriented reorder buffer
App 20020007450 - Witt, David B. ; et al. | 2002-01-17 |
Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
Grant 6,279,107 - Tran August 21, 2 | 2001-08-21 |
Superscalar microprocessor configured to predict return addresses from a return stack storage
Grant 6,269,436 - Tran , et al. July 31, 2 | 2001-07-31 |
Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache
Grant 6,266,752 - Witt , et al. July 24, 2 | 2001-07-24 |
Three state branch history using one bit in a branch prediction mechanism
Grant 6,253,316 - Tran , et al. June 26, 2 | 2001-06-26 |
Dependency table for reducing dependency checking hardware
Grant 6,249,862 - Chinnakonda , et al. June 19, 2 | 2001-06-19 |
Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received
Grant 6,237,082 - Witt , et al. May 22, 2 | 2001-05-22 |
Superscalar microprocessor including a load/store unit, decode units and a reorder buffer to detect dependencies between access to a stack cache and a data cache
Grant 6,192,462 - Tran , et al. February 20, 2 | 2001-02-20 |
Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache
Grant 6,167,510 - Tran December 26, 2 | 2000-12-26 |
Prefetch buffer which stores a pointer indicating an initial predecode position
Grant 6,122,729 - Tran September 19, 2 | 2000-09-19 |
Way prediction logic for cache array
Grant 6,115,792 - Tran September 5, 2 | 2000-09-05 |
Dependency table for reducing dependency checking hardware
Grant 6,108,769 - Chinnakonda , et al. August 22, 2 | 2000-08-22 |
Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address
Grant 6,079,005 - Witt , et al. June 20, 2 | 2000-06-20 |
Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache
Grant 6,079,003 - Witt , et al. June 20, 2 | 2000-06-20 |
Cache holding register for delayed update of a cache line into an instruction cache
Grant 6,076,146 - Tran , et al. June 13, 2 | 2000-06-13 |
Speculative store buffer
Grant 6,065,103 - Tran , et al. May 16, 2 | 2000-05-16 |
Computer system including a microprocessor having a reorder buffer employing last in buffer and last in line indications
Grant 6,032,251 - Tran , et al. February 29, 2 | 2000-02-29 |
Recorder buffer and a method for allocating a fixed amount of storage for instruction results independent of a number of concurrently dispatched instructions
Grant 6,026,482 - Witt , et al. February 15, 2 | 2000-02-15 |
Way prediction logic for cache array
Grant 6,016,533 - Tran January 18, 2 | 2000-01-18 |
Superscalar microprocessor configured to predict return addresses from a return stack storage
Grant 6,014,734 - Tran , et al. January 11, 2 | 2000-01-11 |
Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions
Grant 6,012,125 - Tran January 4, 2 | 2000-01-04 |
Number of pipeline stages and loop length related counter differential based end-loop prediction
Grant 6,003,128 - Tran December 14, 1 | 1999-12-14 |
Branch prediction mechanism employing branch selectors to select a branch prediction
Grant 5,995,749 - Tran November 30, 1 | 1999-11-30 |
Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions
Grant 5,978,906 - Tran November 2, 1 | 1999-11-02 |
Microcode scan unit for scanning microcode instructions using predecode data
Grant 5,968,163 - Narayan , et al. October 19, 1 | 1999-10-19 |
Reorder buffer having a future file for storing speculative instruction execution results
Grant 5,961,634 - Tran October 5, 1 | 1999-10-05 |
Branch selector prediction
Grant 5,954,816 - Tran , et al. September 21, 1 | 1999-09-21 |
System for using a data history table to select among multiple data prefetch algorithms
Grant 5,941,981 - Tran August 24, 1 | 1999-08-24 |
Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations
Grant 5,940,602 - Narayan , et al. August 17, 1 | 1999-08-17 |
Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction
Grant 5,933,618 - Tran , et al. August 3, 1 | 1999-08-03 |
Microprocessor configured to detect memory operations having data addresses indicative of a boundary between instructions sets
Grant 5,930,489 - Bartkowiak , et al. July 27, 1 | 1999-07-27 |
Apparatus and method for modifying status bits in a reorder buffer with a large speculative state
Grant 5,920,710 - Tan , et al. July 6, 1 | 1999-07-06 |
Search mechanism for a rotating pointer buffer
Grant 5,919,251 - Tran July 6, 1 | 1999-07-06 |
Branch misprediction recovery in a reorder buffer having a future file
Grant 5,915,110 - Witt , et al. June 22, 1 | 1999-06-22 |
Multi-chip superscalar microprocessor module
Grant 5,909,587 - Tran June 1, 1 | 1999-06-01 |
Method for transferring data between a pair of caches configured to be accessed from different stages of an instruction processing pipeline
Grant 5,903,910 - Tran , et al. May 11, 1 | 1999-05-11 |
Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions
Grant 5,903,741 - Witt , et al. May 11, 1 | 1999-05-11 |
Storage device having varying access times and a superscalar microprocessor employing the same
Grant 5,900,012 - Tran May 4, 1 | 1999-05-04 |
Microprocessor employing local caches for functional units to store memory operands used by the functional units
Grant 5,898,849 - Tran April 27, 1 | 1999-04-27 |
Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register
Grant 5,892,936 - Tran , et al. April 6, 1 | 1999-04-06 |
Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions
Grant 5,887,152 - Tran March 23, 1 | 1999-03-23 |
Superscalar microprocessor which delays update of branch prediction information in response to branch misprediction until a subsequent idle clock
Grant 5,875,324 - Tran , et al. February 23, 1 | 1999-02-23 |
Reorder buffer having a future file for storing speculative instruction execution results
Grant 5,872,951 - Tran February 16, 1 | 1999-02-16 |
Superscalar microprocessor configured to predict return addresses from a return stack storage
Grant 5,864,707 - Tran , et al. January 26, 1 | 1999-01-26 |
Microprocessor configured to selectively invoke a microcode DSP function or a program subroutine in response to a target address value of branch instruction
Grant 5,864,689 - Tran January 26, 1 | 1999-01-26 |
Instruction alignment using a dispatch list and a latch list
Grant 5,859,992 - Tran , et al. January 12, 1 | 1999-01-12 |
Instruction scanning unit for locating instructions via parallel scanning of start and end byte information
Grant 5,852,727 - Narayan , et al. December 22, 1 | 1998-12-22 |
Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched
Grant 5,850,532 - Narayan , et al. December 15, 1 | 1998-12-15 |
Way prediction unit and a method for operating the same
Grant 5,848,433 - Tran , et al. December 8, 1 | 1998-12-08 |
Prefetch buffer for storing instructions prior to placing the instructions in an instruction cache
Grant 5,845,101 - Johnson , et al. December 1, 1 | 1998-12-01 |
Apparatus for providing memory and register operands concurrently to functional units
Grant 5,835,968 - Mahalingaiah , et al. November 10, 1 | 1998-11-10 |
Microprocessor configured to swap operands in order to minimize dependency checking logic
Grant 5,835,744 - Tran , et al. November 10, 1 | 1998-11-10 |
Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations
Grant 5,832,297 - Ramagopal , et al. November 3, 1 | 1998-11-03 |
Apparatus and method for aligning variable byte-length instructions to a plurality of issue positions
Grant 5,822,559 - Narayan , et al. October 13, 1 | 1998-10-13 |
Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor
Grant 5,822,558 - Tran October 13, 1 | 1998-10-13 |
Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction
Grant 5,822,575 - Tran October 13, 1 | 1998-10-13 |
Shared branch prediction structure
Grant 5,794,028 - Tran August 11, 1 | 1998-08-11 |
Apparatus and method for accessing special registers without serialization
Grant 5,787,266 - Johnson , et al. July 28, 1 | 1998-07-28 |
Microprocessor using an instruction field to define DSP instructions
Grant 5,768,553 - Tran June 16, 1 | 1998-06-16 |
Reorder buffer employing last in buffer and last in line bits
Grant 5,768,555 - Tran , et al. June 16, 1 | 1998-06-16 |
Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
Grant 5,764,946 - Tran , et al. June 9, 1 | 1998-06-09 |
Recorder buffer capable of detecting dependencies between accesses to a pair of caches
Grant 5,765,035 - Tran June 9, 1 | 1998-06-09 |
Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array
Grant 5,761,712 - Tran , et al. June 2, 1 | 1998-06-02 |
Byte queue divided into multiple subqueues for optimizing instruction selection logic
Grant 5,748,978 - Narayan , et al. May 5, 1 | 1998-05-05 |
Register file having multiple register storages for storing data from multiple data streams
Grant 5,713,039 - Tran January 27, 1 | 1998-01-27 |
Cache access system for multiple requestors providing independent access to the cache arrays
Grant 5,483,645 - Tran January 9, 1 | 1996-01-09 |
Apparatus for controlling execution of a program in a computing device
Grant 5,251,306 - Tran October 5, 1 | 1993-10-05 |
Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy
Grant 5,185,868 - Tran February 9, 1 | 1993-02-09 |
Method and apparatus for reducing critical speed path delays
Grant 4,940,908 - Tran July 10, 1 | 1990-07-10 |
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