Tran; Minh Quoc

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tran; Minh Quoc.The latest application filed is for "low-h plasma treatment with n2 anneal for electronic memory devices".

Company Profile

0.10.2

Tran; Minh Quoc - Milpitas CA
Tran; Minh Quoc - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Low-H plasma treatment with N.sub.2 anneal for electronic memory devices Grant 8,202,810 - Nickel , et al. June 19, 2	2012-06-19
Low-h Plasma Treatment With N2 Anneal For Electronic Memory Devices App 20090176369 - Nickel; Alexander H. ; et al.	2009-07-09
Ultra low dielectric constant integrated circuit system Grant 7,256,499 - You , et al. August 14, 2	2007-08-14
Sealing sidewall pores in low-k dielectrics Grant 7,208,418 - Okada , et al. April 24, 2	2007-04-24
Interconnect with multiple layers of conductive material with grain boundary between the layers Grant 7,001,840 - Tran , et al. February 21, 2	2006-02-21
Method for forming dual damascene interconnect structure Grant 6,756,300 - Wang , et al. June 29, 2	2004-06-29
Electro-chemical metal alloying for semiconductor manufacturing Grant 6,649,034 - Tran , et al. November 18, 2	2003-11-18
Method and system for polishing a semiconductor wafer Grant 6,609,946 - Tran August 26, 2	2003-08-26
Method of manufacturing an amorphized barrier layer for integrated circuit interconnects Grant 6,583,051 - Lopatin , et al. June 24, 2	2003-06-24
Imaging of integrated circuit interconnects Grant 6,541,286 - Bernard , et al. April 1, 2	2003-04-01
Plating system with secondary ring anode for a semiconductor wafer Grant 6,425,991 - Tran , et al. July 30, 2	2002-07-30
Method of manufacturing an amorphized barrier layer for integrated circuit interconnects App 20020061644 - Lopatin, Sergey D. ; et al.	2002-05-23

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