Tran; Giap
Patent Applications and Registrations
Patent applications and USPTO patent grants for Tran; Giap.The latest application filed is for "pvt compensation scheme for output buffers".
- Tran; Giap - San Jose CA
Trademarks
| Patent | Date |
|---|---|
| Hot-socket circuitry Grant 9,515,643 - Truong , et al. December 6, 2 | 2016-12-06 |
| PVT compensation scheme for output buffers Grant 9,287,872 - Kee , et al. March 15, 2 | 2016-03-15 |
| PVT Compensation Scheme for Output Buffers App 20150372679 - Kee; Siak Chon ; et al. | 2015-12-24 |
| Hot-Socket Circuitry App 20150194953 - Truong; Keith ; et al. | 2015-07-09 |
| Programmable logic device with a multi-data rate SDRAM interface Grant 7,787,326 - Sharpe-Geisler , et al. August 31, 2 | 2010-08-31 |
| Programmable logic device with power-saving architecture Grant 7,558,143 - Law , et al. July 7, 2 | 2009-07-07 |
| Input/output systems and methods Grant 7,411,419 - Truong , et al. August 12, 2 | 2008-08-12 |
| Programmable logic device with power-saving architecture Grant 7,376,037 - Law , et al. May 20, 2 | 2008-05-20 |
| Programmable logic device with a double data rate SDRAM interface Grant 7,342,838 - Sharpe-Geisler , et al. March 11, 2 | 2008-03-11 |
| Scalable serializer-deserializer architecture and programmable interface Grant 7,098,685 - Agrawal , et al. August 29, 2 | 2006-08-29 |
| I/O buffer architecture for programmable devices Grant 7,061,269 - Agrawal , et al. June 13, 2 | 2006-06-13 |
| Enhanced I/O control flexibility for generating control signals Grant 6,191,612 - Agrawal , et al. February 20, 2 | 2001-02-20 |
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