Tower; Samuel J.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Tower; Samuel J..The latest application filed is for "flip-flop having logic state retention during a power down mode and method therefor".
- Tower; Samuel J. - Austin TX
| Patent | Date |
|---|---|
| Pulsed state retention power gating flip-flop Grant 8,289,060 - Tower , et al. October 16, 2 | 2012-10-16 |
| Flip-flop having logic state retention during a power down mode and method therefor Grant 7,583,121 - Berzins , et al. September 1, 2 | 2009-09-01 |
| Flip-flop Having Logic State Retention During A Power Down Mode And Method Therefor App 20090058485 - Berzins; Matthew S. ; et al. | 2009-03-05 |
| Pulsed State Retention Power Gating Flip-flop App 20080315932 - Tower; Samuel J. ; et al. | 2008-12-25 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 