Toutounchi; Shahin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Toutounchi; Shahin.The latest application filed is for "application-specific testing methods for programmable logic devices".

Company Profile

0.25.1

Toutounchi; Shahin - Pleasanton CA

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Patent Activity

Patent	Date
Manufacturing test for a programmable integrated circuit implementing a specific user design Grant 8,311,762 - Hartanto , et al. November 13, 2	2012-11-13
Non-volatile memory cell with charge storage element and method of programming Grant 7,947,980 - Toutounchi , et al. May 24, 2	2011-05-24
Testing an embedded core Grant 7,917,820 - Pavle , et al. March 29, 2	2011-03-29
Circuit for and method of testing for faults in a programmable logic device Grant 7,761,755 - Payakapan , et al. July 20, 2	2010-07-20
Testing of a programmable device Grant 7,725,787 - Wells , et al. May 25, 2	2010-05-25
Three-terminal non-volatile memory element with hybrid gate dielectric Grant 7,687,797 - Karp , et al. March 30, 2	2010-03-30
Non-volatile memory cell with charge storage element and method of programming Grant 7,544,968 - Toutounchi , et al. June 9, 2	2009-06-09
Testing of a programmable device Grant 7,454,675 - Wells , et al. November 18, 2	2008-11-18
Single event upset in SRAM cells in FPGAs with high resistivity gate structures Grant 7,452,765 - Voogel , et al. November 18, 2	2008-11-18
PMOS three-terminal non-volatile memory element and method of programming Grant 7,450,431 - Karp , et al. November 11, 2	2008-11-11
Method of programming a three-terminal non-volatile memory element using source-drain bias Grant 7,420,842 - Ahrens , et al. September 2, 2	2008-09-02
Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration Grant 7,302,625 - Payakapan , et al. November 27, 2	2007-11-27
Automated fault diagnosis in a programmable device Grant 7,219,287 - Toutounchi , et al. May 15, 2	2007-05-15
Single event upset in SRAM cells in FPGAs with high resistivity gate structures Grant 6,982,451 - Voogel , et al. January 3, 2	2006-01-03
Methods of testing for shorts in programmable logic devices using relative quiescent current measurements Grant 6,920,621 - Toutounchi , et al. July 19, 2	2005-07-19
Application-specific testing methods for programmable logic devices Grant 6,891,395 - Wells , et al. May 10, 2	2005-05-10
Application-specific testing methods for programmable logic devices Grant 6,817,006 - Wells , et al. November 9, 2	2004-11-09
Application-specific testing methods for programmable logic devices App 20040216081 - Wells, Robert W. ; et al.	2004-10-28
Method for testing faults in a programmable logic device Grant 6,732,309 - Toutounchi , et al. May 4, 2	2004-05-04
Method for locating faults in a programmable logic device Grant 6,732,348 - Tahoori , et al. May 4, 2	2004-05-04
Method of forming a zener diode Grant 6,645,802 - Li , et al. November 11, 2	2003-11-11
Fault emulation testing of programmable logic devices Grant 6,594,610 - Toutounchi , et al. July 15, 2	2003-07-15
Non-volatile memory array using gate breakdown structures Grant 6,522,582 - Rao , et al. February 18, 2	2003-02-18
Three terminal non-volatile memory element Grant 6,266,269 - Karp , et al. July 24, 2	2001-07-24
Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process Grant 6,044,012 - Rao , et al. March 28, 2	2000-03-28
High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance Grant 5,516,731 - Toutounchi , et al. May 14, 1	1996-05-14

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