Torres; Victor

Patent Applications and Registrations

Patent applications and USPTO patent grants for Torres; Victor.The latest application filed is for "electronic system".

Company Profile

2.11.5

Torres; Victor - Barcelona ES
Torres; Victor - Schenectady NY
Torres; Victor - Midland MI
Torres; Victor - Irving TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks

Patent Activity

Patent	Date
Electronic System App 20210138168 - Torres; Victor ; et al.	2021-05-13
Inhaler Grant D882,754 - Turner , et al.	2020-04-28
Sputtering system and method for forming a metal layer on a semiconductor device Grant 10,354,871 - Kennerly , et al. July 16, 2	2019-07-16
Sputtering System And Method For Forming A Metal Layer On A Semiconductor Device App 20190080906 - Kennerly; Stacey Joy ; et al.	2019-03-14
Method for manufacturing SiC wafer fit for integration with power device manufacturing technology Grant 10,002,760 - Hansen , et al. June 19, 2	2018-06-19
METHOD FOR MANUFACTURING SiC WAFER FIT FOR INTEGRATION WITH POWER DEVICE MANUFACTURING TECHNOLOGY App 20160189956 - Hansen; Darren ; et al.	2016-06-30
Method for manufacturing SiC wafer fit for integration with power device manufacturing technology Grant 9,279,192 - Hansen , et al. March 8, 2	2016-03-08
Method For Manufacturing Sic Wafer Fit For Integration With Power Device Manufacturing Technology App 20160032486 - Hansen; Darren ; et al.	2016-02-04
Method to manufacture large uniform ingots of silicon carbide by sublimation/condensation processes Grant 8,765,091 - Loboda , et al. July 1, 2	2014-07-01
Method to Manufacture Large Uniform Ingots of Silicon Carbide by Sublimation/Condensation Processes App 20120114545 - Loboda; Mark ; et al.	2012-05-10
System and method for providing a dual via architecture for thin film resistors Grant 7,960,240 - Hill , et al. June 14, 2	2011-06-14
System and method for providing a buried thin film resistor having end caps defined by a dielectric mask Grant 7,808,048 - Hill , et al. October 5, 2	2010-10-05
System and method for faceting a masking layer in a plasma etch to slope a feature edge Grant 7,585,775 - Bold , et al. September 8, 2	2009-09-08
System and method for providing a dual via architecture for thin film resistors Grant 7,410,879 - Hill , et al. August 12, 2	2008-08-12
System and method for providing a buried thin film resistor having end caps defined by a dielectric mask Grant 7,332,403 - Hill , et al. February 19, 2	2008-02-19

Company Registrations

NCAGE Code	6VL11	TORRES, VICTOR!DBA CLEANWORLD SYSTEM
CAGE Code	6VL11	TORRES, VICTOR CLEANWORLD SYSTEM
DUNS	045347518	Torres, Victor

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