Torres; Jessica
Patent Applications and Registrations
Patent applications and USPTO patent grants for Torres; Jessica.The latest application filed is for "self-aligned interconnect structures and methods of fabrication".
- Torres; Jessica - Portland OR
- Torres; Jessica - San Francisco CA
| Patent | Date |
|---|---|
| Self-aligned Interconnect Structures And Methods Of Fabrication App 20220199468 - Jun; Kimin ; et al. | 2022-06-23 |
| Integrated Circuit Structures Having Gesnb Source Or Drain Structures App 20220190159 - PAUL; Rajat ; et al. | 2022-06-16 |
| Gate-all-around Integrated Circuit Structures Having Strained Dual Nanoribbon Channel Structures App 20210407996 - AGRAWAL; Ashish ; et al. | 2021-12-30 |
| Plasma Nitridation For Gate Oxide Scaling Of Ge And Sige Transistors App 20210408239 - CHOUKSEY; Siddharth ; et al. | 2021-12-30 |
| Display screen with graphical user interface Grant D915,420 - Saigal , et al. April 6, 2 | 2021-04-06 |
| Self-aligned Gate Endcap (sage) Architectures Without Fin End Gap App 20210091075 - LIAO; Szuya S. ; et al. | 2021-03-25 |
| Source Or Drain Structures For Germanium N-channel Devices App 20200313001 - KEECH; Ryan ; et al. | 2020-10-01 |
| Channel Layer For Iii-v Metal-oxide-semiconductor Field Effect Transistors (mosfets) App 20200006523 - METZ; Matthew ; et al. | 2020-01-02 |
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