Topaloglu; Rasit O.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Topaloglu; Rasit O..The latest application filed is for "volumetric display-based captcha system".
Company Profile
11.42.38
- Topaloglu; Rasit O. - Poughkeepsie NY
- Topaloglu; Rasit O - Poughkeepsie NY
- Topaloglu; Rasit O. - Pougkeepsie NY
- Topaloglu; Rasit O. - Santa Clara CA US
Patent Activity
| Patent | Date |
|---|---|
| Two dimension material fin sidewall Grant 11,424,365 - Rosenblatt , et al. August 23, 2 | 2022-08-23 |
| Airgap vias in electrical interconnects Grant 11,011,415 - Topaloglu , et al. May 18, 2 | 2021-05-18 |
| Spoken microagreements with blockchain Grant 10,916,253 - Topaloglu February 9, 2 | 2021-02-09 |
| Integrated circuit security Grant 10,896,883 - Lai , et al. January 19, 2 | 2021-01-19 |
| Volumetric Display-based Captcha System App 20200410081 - Topaloglu; Rasit O ; et al. | 2020-12-31 |
| Fluxonium qubits and devices including plurality of vertical stacks of Josephson junctions Grant 10,840,295 - Sandberg , et al. November 17, 2 | 2020-11-17 |
| Fluxonium Qubit And Devices Including Plurality Of Vertical Stacks Of Josephson Junctions App 20200335549 - Sandberg; Martin O. ; et al. | 2020-10-22 |
| Magnetic Tunnel Junction Based True Random Number Generator App 20200326911 - Topaloglu; Rasit O. ; et al. | 2020-10-15 |
| Backside coupling with superconducting partial TSV for transmon qubits Grant 10,804,454 - Hertzberg , et al. October 13, 2 | 2020-10-13 |
| Airgap vias in electrical interconnects Grant 10,796,949 - Topaloglu , et al. October 6, 2 | 2020-10-06 |
| Airgap Vias In Electrical Interconnects App 20200258770 - A1 | 2020-08-13 |
| Two Dimension Material Fin Sidewall App 20200219873 - Rosenblatt; Sami ; et al. | 2020-07-09 |
| Persistent flux biasing methodology for superconducting loops Grant 10,665,635 - Sandberg , et al. | 2020-05-26 |
| Integrated Circuit Security App 20200144203 - Lai; Kafai ; et al. | 2020-05-07 |
| Spoken Microagreements With Blockchain App 20200135207 - TOPALOGLU; Rasit O. | 2020-04-30 |
| Airgap Vias In Electrical Interconnects App 20200126842 - Topaloglu; Rasit O. ; et al. | 2020-04-23 |
| Two dimension material fin sidewall Grant 10,580,772 - Rosenblatt , et al. | 2020-03-03 |
| Integrated circuit security Grant 10,573,606 - Lai , et al. Feb | 2020-02-25 |
| Backside Coupling With Superconducting Partial Tsv For Transmon Qubits App 20200052181 - Hertzberg; Jared Barney ; et al. | 2020-02-13 |
| Two dimension material fin sidewall Grant 10,559,564 - Rosenblatt , et al. Feb | 2020-02-11 |
| Vertical superconducting capacitors for transmon qubits Grant 10,552,758 - Hertzberg , et al. Fe | 2020-02-04 |
| Backside coupling with superconducting partial TSV for transmon qubits Grant 10,529,908 - Hertzberg , et al. J | 2020-01-07 |
| Vertical superconducting capacitors for transmon qubits Grant 10,445,651 - Hertzberg , et al. Oc | 2019-10-15 |
| Backside coupling with superconducting partial TSV for transmon qubits Grant 10,446,736 - Hertzberg , et al. Oc | 2019-10-15 |
| Wire lineend to via overlap optimization Grant 10,394,992 - Topaloglu A | 2019-08-27 |
| Vertical Superconducting Capacitors For Transmon Qubits App 20190228334 - Hertzberg; Jared Barney ; et al. | 2019-07-25 |
| Backside Coupling With Superconducting Partial Tsv For Transmon Qubits App 20190181325 - Hertzberg; Jared Barney ; et al. | 2019-06-13 |
| Integrated Circuit Security App 20190172798 - Lai; Kafai ; et al. | 2019-06-06 |
| Integrated circuit security Grant 10,312,200 - Lai , et al. | 2019-06-04 |
| Backside Coupling With Superconducting Partial Tsv For Transmon Qubits App 20190165237 - Hertzberg; Jared Barney ; et al. | 2019-05-30 |
| Wire Lineend To Via Overlap Optimization App 20190138681 - Topaloglu; Rasit O. | 2019-05-09 |
| Vertical Superconducting Capacitors For Transmon Qubits App 20190130302 - Hertzberg; Jared Barney ; et al. | 2019-05-02 |
| Integrated Circuit Security App 20190035746 - Lai; Kafai ; et al. | 2019-01-31 |
| Two dimension material fin sidewall Grant 10,170,474 - Rosenblatt , et al. J | 2019-01-01 |
| Multiple-depth trench interconnect technology at advanced semiconductor nodes Grant 10,169,525 - Greco , et al. J | 2019-01-01 |
| Early overlay prediction and overlay-aware mask design Grant 10,152,567 - Greco , et al. Dec | 2018-12-11 |
| Two Dimension Material Fin Sidewall App 20180342510 - Rosenblatt; Sami ; et al. | 2018-11-29 |
| Two Dimension Material Fin Sidewall App 20180342511 - Rosenblatt; Sami ; et al. | 2018-11-29 |
| Dynamic intrinsic chip identification Grant 10,142,335 - Kothandaraman , et al. Nov | 2018-11-27 |
| Two Dimension Material Fin Sidewall App 20180301448 - Rosenblatt; Sami ; et al. | 2018-10-18 |
| Two Dimension Material Fin Sidewall App 20180301449 - Rosenblatt; Sami ; et al. | 2018-10-18 |
| Two Dimension Material Fin Sidewall App 20180301450 - Rosenblatt; Sami ; et al. | 2018-10-18 |
| Two dimension material fin sidewall Grant 10,103,145 - Rosenblatt , et al. October 16, 2 | 2018-10-16 |
| Two dimension material fin sidewall Grant 10,103,144 - Rosenblatt , et al. October 16, 2 | 2018-10-16 |
| Vertical superconducting capacitors for transmon qubits Grant 10,068,184 - Hertzberg , et al. September 4, 2 | 2018-09-04 |
| Reliability of an electronic device Grant 10,042,969 - Liebmann , et al. August 7, 2 | 2018-08-07 |
| Early Overlay Prediction And Overlay-aware Mask Design App 20180129774 - Greco; Stephen E. ; et al. | 2018-05-10 |
| Two dimension material fin sidewall Grant 9,947,660 - Rosenblatt , et al. April 17, 2 | 2018-04-17 |
| Early overlay prediction and overlay-aware mask design Grant 9,940,429 - Greco , et al. April 10, 2 | 2018-04-10 |
| Bottom self-aligned via Grant 9,859,208 - Angyal , et al. January 2, 2 | 2018-01-02 |
| Stacked carbon nanotube multiple threshold device Grant 9,837,491 - Rosenblatt , et al. December 5, 2 | 2017-12-05 |
| Multiple-depth Trench Interconnect Technology At Advanced Semiconductor Nodes App 20170277823 - Greco; Stephen E. ; et al. | 2017-09-28 |
| Multiple-depth trench interconnect technology at advanced semiconductor nodes Grant 9,710,592 - Greco , et al. July 18, 2 | 2017-07-18 |
| Dynamic Intrinsic Chip Identification App 20170180369 - Kothandaraman; Chandrasekharan ; et al. | 2017-06-22 |
| Stacked Carbon Nanotube Multiple Threshold Device App 20170170267 - Rosenblatt; Sami ; et al. | 2017-06-15 |
| Interconnect level structures for confining stitch-induced via structures Grant 9,601,367 - Greco , et al. March 21, 2 | 2017-03-21 |
| Reliability Of An Electronic Device App 20170061062 - LIEBMANN; LARS W. ; et al. | 2017-03-02 |
| Mask decomposition and optimization for directed self assembly Grant 9,569,578 - Lai , et al. February 14, 2 | 2017-02-14 |
| Early Overlay Prediction And Overlay-aware Mask Design App 20160378904 - Greco; Stephen E. ; et al. | 2016-12-29 |
| Stitch-derived via structures and methods of generating the same Grant 9,454,631 - Greco , et al. September 27, 2 | 2016-09-27 |
| Dividing lithography exposure fields to improve semiconductor fabrication Grant 9,424,388 - Greco , et al. August 23, 2 | 2016-08-23 |
| Dividing Lithography Exposure Fields To Improve Semiconductor Fabrication App 20160180003 - Greco; Stephen E. ; et al. | 2016-06-23 |
| Interconnect level structures for confining stitch-induced via structures Grant 9,373,538 - Greco , et al. June 21, 2 | 2016-06-21 |
| Multiple-depth Trench Interconnect Technology At Advancedsemiconductor Nodes App 20160042114 - Greco; Stephen E. ; et al. | 2016-02-11 |
| Interconnect Level Structures For Confining Stitch-induced Via Structures App 20160027687 - Greco; Stephen E. ; et al. | 2016-01-28 |
| Stitch-derived Via Structures And Methods Of Generating The Same App 20150339422 - Greco; Stephen E. ; et al. | 2015-11-26 |
| Integrated circuit systems including vertical inductors Grant 9,159,711 - Topaloglu October 13, 2 | 2015-10-13 |
| Reticle data decomposition for focal plane determination in lithographic processes Grant 9,058,457 - Greco , et al. June 16, 2 | 2015-06-16 |
| Reticle Data Decomposition For Focal Plane Determination In Lithographic Processes App 20150143305 - Greco; Stephen E. ; et al. | 2015-05-21 |
| Interconnect Level Structures For Confining Stitch-induced Via Structures App 20140284813 - Greco; Stephen E. ; et al. | 2014-09-25 |
| Generation of design shapes for confining stitch-induced via structures Grant 8,806,393 - Greco , et al. August 12, 2 | 2014-08-12 |
| Integrated Circuit Systems Including Vertical Inductors App 20130027127 - Topaloglu; Rasit O. | 2013-01-31 |
| Work balancing scheduler for processor cores and methods thereof Grant 8,219,994 - Topaloglu July 10, 2 | 2012-07-10 |
| Two-step simulation methodology for aging simulations Grant 8,099,269 - Topaloglu , et al. January 17, 2 | 2012-01-17 |
| Scheduler For Processor Cores And Methods Thereof App 20100107166 - Topaloglu; Rasit O. | 2010-04-29 |
| Double layer stress for multiple gate transistors Grant 7,671,418 - Topaloglu March 2, 2 | 2010-03-02 |
| Two-step Simulation Methodology For Aging Simulations App 20090094013 - TOPALOGLU; Rasit O. ; et al. | 2009-04-09 |
| Double Layer Stress For Multiple Gate Transistors App 20090072316 - TOPALOGLU; Rasit O. | 2009-03-19 |
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