| Patent | Date |
|---|
Integrated circuit product customizations for identification code visibility
Grant 11,315,883 - Hu , et al. April 26, 2 | 2022-04-26 |
Integrated Circuit Product Customizations For Identification Code Visibility
App 20210143104 - Hu; Suming ; et al. | 2021-05-13 |
Circuit board with constrained solder interconnect pads
Grant 10,431,533 - Topacio , et al. O | 2019-10-01 |
Circuit Board With Constrained Solder Interconnect Pads
App 20160126171 - Topacio; Roden ; et al. | 2016-05-05 |
Thermal management circuit board for stacked semiconductor chip device
Grant 9,209,106 - Shi , et al. December 8, 2 | 2015-12-08 |
Routing layer for mitigating stress in a semiconductor die
Grant 9,059,159 - Topacio , et al. June 16, 2 | 2015-06-16 |
Routing layer for mitigating stress in a semiconductor die
Grant 9,035,471 - Topacio , et al. May 19, 2 | 2015-05-19 |
Die substrate with reinforcement structure
Grant 8,927,344 - Topacio , et al. January 6, 2 | 2015-01-06 |
Routing Layer For Mitigating Stress In A Semiconductor Die
App 20140167261 - Topacio; Roden ; et al. | 2014-06-19 |
Routing Layer For Mitigating Stress In A Semiconductor Die
App 20140110837 - Topacio; Roden ; et al. | 2014-04-24 |
Routing layer for mitigating stress in a semiconductor die
Grant 8,664,777 - Topacio , et al. March 4, 2 | 2014-03-04 |
Routing layer for mitigating stress in a semiconductor die
Grant 8,642,463 - Topacio , et al. February 4, 2 | 2014-02-04 |
Semiconductor chip with underfill anchors
Grant 8,633,599 - Topacio , et al. January 21, 2 | 2014-01-21 |
Thermal Management Circuit Board For Stacked Semiconductor Chip Device
App 20130343000 - Shi; Xiao Ling ; et al. | 2013-12-26 |
Semiconductor Chip With Underfill Anchors
App 20130154122 - Topacio; Roden ; et al. | 2013-06-20 |
Die Substrate With Reinforcement Structure
App 20130069250 - Topacio; Roden ; et al. | 2013-03-21 |
Routing Layer For Mitigating Stress In A Semiconductor Die
App 20130032941 - Topacio; Roden ; et al. | 2013-02-07 |
Die substrate with reinforcement structure
Grant 8,313,984 - Topacio , et al. November 20, 2 | 2012-11-20 |
Routing layer for mitigating stress in a semiconductor die
Grant 8,299,632 - Topacio , et al. October 30, 2 | 2012-10-30 |
Routing Layer For Mitigating Stress In A Semiconductor Die
App 20120270388 - Topacio; Roden ; et al. | 2012-10-25 |
Routing layer for mitigating stress in a semiconductor die
Grant 8,227,926 - Topacio , et al. July 24, 2 | 2012-07-24 |
Routing Layer For Mitigating Stress In A Semiconductor Die
App 20110254154 - Topacio; Roden ; et al. | 2011-10-20 |
Method Of Manufacturing Substrates Having Asymmetric Buildup Layers
App 20110225813 - Leung; Andrew ; et al. | 2011-09-22 |
Method and apparatus for making semiconductor packages
Grant 7,985,621 - Chan , et al. July 26, 2 | 2011-07-26 |
Circuit Board with Variable Topography Solder Interconnects
App 20110100692 - Topacio; Roden ; et al. | 2011-05-05 |
Routing Layer For Mitigating Stress In A Semiconductor Die
App 20110095415 - Topacio; Roden ; et al. | 2011-04-28 |
Method Of Manufacturing Substrates Having Asymmetric Buildup Layers
App 20110024898 - Leung; Andrew ; et al. | 2011-02-03 |
Die substrate with reinforcement structure
App 20090236730 - Topacio; Roden ; et al. | 2009-09-24 |
Flip-Chip Semiconductor Package with Encapsulant Retaining Structure and Strip
App 20080099910 - McLellan; Neil ; et al. | 2008-05-01 |
Method And Apparatus For Making Semiconductor Packages
App 20080057625 - Chan; Vincent K. ; et al. | 2008-03-06 |
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