Tonti; William Robert

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tonti; William Robert.The latest application filed is for "layered structure with fuse".

Company Profile

0.53.63

Tonti; William Robert - Essex Junction VT
Tonti; William Robert - Essex Junctiion VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High-voltage silicon-on-insulator transistors and methods of manufacturing the same Grant 8,772,876 - Ma , et al. July 8, 2	2014-07-08
Layered structure with fuse Grant 8,610,244 - Lu-Chen Hsu , et al. December 17, 2	2013-12-17
Layered Structure With Fuse App 20120248567 - Lu-Chen Hsu; Louis ; et al.	2012-10-04
Electronic fuses in semiconductor integrated circuits Grant 8,232,620 - Lu-Chen Hsu , et al. July 31, 2	2012-07-31
Method and system for selective stress enablement in simulation modeling Grant 8,112,729 - Tonti , et al. February 7, 2	2012-02-07
Enhanced stress-retention fin-FET devices and methods of fabricating enhanced stress retention fin-FET devices Grant 8,084,822 - Chatty , et al. December 27, 2	2011-12-27
Semiconductor transistors with contact holes close to gates Grant 7,985,643 - Furukawa , et al. July 26, 2	2011-07-26
Structures incorporating interconnect structures with improved electromigration resistance Grant 7,984,409 - Hsu , et al. July 19, 2	2011-07-19
Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes Grant 7,919,347 - Cheng , et al. April 5, 2	2011-04-05
Enhanced Stress-retention Fin-fet Devices And Methods Of Fabricating Enhanced Stress Retention Fin-fet Devices App 20110073951 - Chatty; Kiran V. ; et al.	2011-03-31
Thin gate electrode CMOS devices and methods of fabricating same Grant 7,906,390 - Mandelman , et al. March 15, 2	2011-03-15
Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Grant 7,879,660 - Booth, Jr. , et al. February 1, 2	2011-02-01
Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates Grant 7,875,960 - Hsu , et al. January 25, 2	2011-01-25
Electronic Fuses In Semiconductor Integrated Circuits App 20100320563 - Lu-Chen Hsu; Louis ; et al.	2010-12-23
Method And System For Selective Stress Enablement In Simulation Modeling App 20100269075 - Tonti; William Robert ; et al.	2010-10-21
Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates Grant 7,818,702 - Mandelman , et al. October 19, 2	2010-10-19
Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures Grant 7,791,145 - Furukawa , et al. September 7, 2	2010-09-07
High-voltage silicon-on-insulator transistors and methods of manufacturing the same Grant 7,790,527 - Ma , et al. September 7, 2	2010-09-07
Electronic fuses in semiconductor integrated circuits Grant 7,785,934 - Hsu , et al. August 31, 2	2010-08-31
Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures Grant 7,754,513 - Mandelman , et al. July 13, 2	2010-07-13
Methods Of Fabricating P-i-n Diodes, Structures For P-i-n Diodes And Design Structure For P-i-n Diodes App 20100173449 - Cheng; Kangguo ; et al.	2010-07-08
Design structure incorporating a hybrid substrate Grant 7,750,406 - Cannon , et al. July 6, 2	2010-07-06
Well isolation trenches (WIT) for CMOS devices Grant 7,737,504 - Furukawa , et al. June 15, 2	2010-06-15
Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices Grant 7,737,498 - Chatty , et al. June 15, 2	2010-06-15
Methods and semiconductor structures for latch-up suppression using a conductive region Grant 7,727,848 - Furukawa , et al. June 1, 2	2010-06-01
Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Grant 7,692,250 - Booth, Jr. , et al. April 6, 2	2010-04-06
Interconnect structures with improved electromigration resistance and methods for forming such interconnect structures Grant 7,666,781 - Hsu , et al. February 23, 2	2010-02-23
Methods and semiconductor structures for latch-up suppression using a conductive region Grant 7,655,985 - Furukawa , et al. February 2, 2	2010-02-02
Hybrid substrates and methods for forming such hybrid substrates Grant 7,651,902 - Cannon , et al. January 26, 2	2010-01-26
Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates Grant 7,651,929 - Hsu , et al. January 26, 2	2010-01-26
Method of fabricating semiconductor structures for latch-up suppression Grant 7,648,869 - Chang , et al. January 19, 2	2010-01-19
Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures Grant 7,645,676 - Furukawa , et al. January 12, 2	2010-01-12
Enhanced Stress-retention Silicon-on-insulator Devices And Methods Of Fabricating Enhanced Stress Retention Silicon-on-insulator Devices App 20090278201 - Chatty; Kiran V. ; et al.	2009-11-12
Monitoring Ionizing Radiation In Silicon-on Insulator Integrated Circuits App 20090113357 - Abadeer; Wagdi William ; et al.	2009-04-30
Design structures incorporating interconnect structures with liner repair layers Grant 7,494,916 - Hsu , et al. February 24, 2	2009-02-24
Methods and semiconductor structures for latch-up suppression using a conductive region Grant 7,491,618 - Furukawa , et al. February 17, 2	2009-02-17
Thin Gate Electrode Cmos Devices And Methods Of Fabricating Same App 20090020827 - Mandelman; Jack A. ; et al.	2009-01-22
Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates Grant 7,473,985 - Hsu , et al. January 6, 2	2009-01-06
Device for monitoring ionizing radiation in silicon-on insulator integrated circuits Grant 7,473,904 - Abadeer , et al. January 6, 2	2009-01-06
Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures App 20090001477 - Hsu; Louis Lu-Chen ; et al.	2009-01-01
Integrated Fin-Local Interconnect Structure App 20090001426 - Cheng; Kangguo ; et al.	2009-01-01
Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures App 20090007037 - Hsu; Louis Lu-Chen ; et al.	2009-01-01
Digital Circuits Having Additional Capacitors For Additional Stability App 20090001481 - Cannon; Ethan Harrison ; et al.	2009-01-01
Integrated Fin-Local Interconnect Structure App 20090007036 - Cheng; Kangguo ; et al.	2009-01-01
Hybrid Oriented Substrates And Crystal Imprinting Methods For Forming Such Hybrid Oriented Substrates App 20080283920 - Hsu; Louis Lu-Chen ; et al.	2008-11-20
Methods And Semiconductor Structures For Latch-up Suppression Using A Conductive Region App 20080268610 - Furukawa; Toshiharu ; et al.	2008-10-30
Hybrid Substrates and Methods for Forming Such Hybrid Substrates App 20080258181 - Cannon; Ethan Harrison ; et al.	2008-10-23
Design Structure Incorporating a Hybrid Substrate App 20080258222 - Cannon; Ethan Harrison ; et al.	2008-10-23
Methods For Fabricating Semiconductor Device Structures With Reduced Susceptibility To Latch-up And Semiconductor Device Structures Formed By The Methods App 20080242016 - Cannon; Ethan Harrison ; et al.	2008-10-02
Latch-Up Resistant Semiconductor Structures on Hybrid Substrates and Methods for Forming Such Semiconductor Structures App 20080217690 - Mandelman; Jack Allan ; et al.	2008-09-11
Methods And Semiconductor Structures For Latch-up Suppression Using A Conductive Region App 20080217698 - Furukawa; Toshiharu ; et al.	2008-09-11
Methods For Fabricating Semiconductor Device Structures With Reduced Susceptibility To Latch-up And Semiconductor Device Structures Formed By The Methods App 20080203492 - Cannon; Ethan Harrison ; et al.	2008-08-28
Electronic Fuses In Semiconductor Integrated Circuits App 20080206978 - Hsu; Louis Lu-Chen ; et al.	2008-08-28
Structure Incorporating Latch-Up Resistant Semiconductor Device Structures on Hybrid Substrates App 20080203522 - Mandelman; Jack Allan ; et al.	2008-08-28
Semiconductor Transistors With Contact Holes Close To Gates App 20080166863 - Furukawa; Toshiharu ; et al.	2008-07-10
Interconnect structures with linear repair layers and methods for forming such interconnection structures Grant 7,396,762 - Hsu , et al. July 8, 2	2008-07-08
Crystal Imprinting Methods For Fabricating Substrates With Thin Active Silicon Layers App 20080146006 - Hsu; Louis Lu-Chen ; et al.	2008-06-19
Monitoring Ionizing Radiation In Silicon-on Insulator Integrated Circuits App 20080128629 - Abadeer; Wagdi William ; et al.	2008-06-05
Interconnect Structures with Liner Repair Layers and Methods for Forming Such Interconnection Structures App 20080122090 - Hsu; Louis Lu-Chen ; et al.	2008-05-29
Design Structures Incorporating Interconnect Structures with Improved Electromigration Resistance App 20080120580 - Hsu; Louis Lu-Chen ; et al.	2008-05-22
Interconnect Structures with Improved Electromigration Resistance and Methods for Forming Such Interconnect Structures App 20080116582 - Hsu; Louis Lu-Chen ; et al.	2008-05-22
Monitoring ionizing radiation in silicon-on insulator integrated circuits Grant 7,375,339 - Abadeer , et al. May 20, 2	2008-05-20
Crystal imprinting methods for fabricating substrates with thin active silicon layers Grant 7,358,164 - Hsu , et al. April 15, 2	2008-04-15
Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures Grant 7,352,034 - Booth, Jr. , et al. April 1, 2	2008-04-01
Design Structures Incorporating Interconnect Structures with Liner Repair Layers App 20080059924 - Hsu; Louis Lu-Chen ; et al.	2008-03-06
Semiconductor Structures For Latch-up Suppression And Methods Of Forming Such Semiconductor Structures App 20080057671 - Furukawa; Toshiharu ; et al.	2008-03-06
Semiconductor Structures Integrating Damascene-body Finfet's And Planar Devices On A Common Substrate And Methods For Forming Such Semiconductor Structures App 20080048265 - Booth; Roger Allen JR. ; et al.	2008-02-28
Semiconductor Structures Integrating Damascene-body Finfet's And Planar Devices On A Common Substrate And Methods For Forming Such Semiconductor Structures App 20080050866 - Booth; Roger Allen JR. ; et al.	2008-02-28
High-voltage Silicon-on-insulator Transistors And Methods Of Manufacturing The Same App 20080048263 - Ma; William Hsioh-Lien ; et al.	2008-02-28
Hybrid Oriented Substrates And Crystal Imprinting Methods For Forming Such Hybrid Oriented Substrates App 20080050890 - Hsu; Louis Lu-Chen ; et al.	2008-02-28
E-Fuse and Method for Fabricating E-Fuses Integrating Polysilicon Resistor Masks App 20080029843 - Booth; Roger Allen JR. ; et al.	2008-02-07
Programmable Semiconductor Device App 20070298526 - Berry; Wayne S. ; et al.	2007-12-27
E-fuse And Method For Fabricating E-fuses Integrating Polysilicon Resistor Masks App 20070262413 - Booth; Roger Allen JR. ; et al.	2007-11-15
Monitoring Ionizing Radiation In Silicon-on Insulator Integrated Circuits App 20070252088 - Abadeer; Wagdi William ; et al.	2007-11-01
Semiconductor Structures For Latch-up Suppression And Methods Of Forming Such Semiconductor Structures App 20070241409 - Furukawa; Toshiharu ; et al.	2007-10-18
Well Isolation Trenches (wit) For Cmos Devices App 20070241408 - Furukawa; Toshiharu ; et al.	2007-10-18
Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures Grant 7,276,768 - Furukawa , et al. October 2, 2	2007-10-02
Intrinsic dual gate oxide MOSFET using a damascene gate process Grant 7,276,775 - Bertin , et al. October 2, 2	2007-10-02
Well isolation trenches (WIT) for CMOS devices Grant 7,268,028 - Furukawa , et al. September 11, 2	2007-09-11
Programmable anti-fuse structures, methods for fabricating programmable anti-fuse structures, and methods of programming anti-fuse structures App 20070205485 - Hsu; Louis Lu-Chen ; et al.	2007-09-06
Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods App 20070194403 - Cannon; Ethan Harrison ; et al.	2007-08-23
Enhanced Silicon-on-insulator (soi) Transistors And Methods Of Making Enhanced Soi Transistors App 20070190740 - Furukawa; Toshiharu ; et al.	2007-08-16
High-voltage silicon-on-insulator transistors and methods of manufacturing the same App 20070182030 - Ma; William Hsioh-Lien ; et al.	2007-08-09
Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors Grant 7,250,351 - Furukawa , et al. July 31, 2	2007-07-31
Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures App 20070170518 - Furukawa; Toshiharu ; et al.	2007-07-26
Methods and semiconductor structures for latch-up suppression using a conductive region App 20070170543 - Furukawa; Toshiharu ; et al.	2007-07-26
Methods and semiconductor structures for latch-up suppression using a buried damage layer App 20070158779 - Cannon; Ethan Harrison ; et al.	2007-07-12
Methods and semiconductor structures for latch-up suppression using a buried conductive region App 20070158755 - Chang; Shunhua Thomas ; et al.	2007-07-12
Resettable fuse device and method of fabricating the same Grant 7,227,239 - Abadeer , et al. June 5, 2	2007-06-05
Semiconductor Transistors With Contact Holes Close To Gates App 20070102766 - Furukawa; Toshiharu ; et al.	2007-05-10
Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures App 20070045748 - Booth; Roger Allen JR. ; et al.	2007-03-01
Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates App 20060284250 - Hsu; Louis Lu-Chen ; et al.	2006-12-21
Crystal imprinting methods for fabricating subsrates with thin active silicon layers App 20060286781 - Hsu; Louis Lu-Chen ; et al.	2006-12-21
Methods of implementing and enhanced silicon-on-insulator (SOI) box structures Grant 7,129,138 - Furukawa , et al. October 31, 2	2006-10-31
Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors App 20060231892 - Furukawa; Toshiharu ; et al.	2006-10-19
Methods Of Implementing And Enhanced Silicon-on-insulator (soi) Box Structures App 20060234428 - Furukawa; Toshiharu ; et al.	2006-10-19
On-chip Cooling App 20060145356 - Liu; Hsichang ; et al.	2006-07-06
Resettable fuse device and method of fabricating the same App 20060060938 - Abadeer; Wagdi William ; et al.	2006-03-23
Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality Grant 6,943,452 - Bertin , et al. September 13, 2	2005-09-13
Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof Grant 6,818,487 - Hsu , et al. November 16, 2	2004-11-16
Structure and method of providing reduced programming voltage antifuse App 20040051162 - Chidambarrao, Dureseti ; et al.	2004-03-18
Wordline on and off voltage compensation circuit based on the array device threshold voltage Grant 6,693,843 - Maffitt , et al. February 17, 2	2004-02-17
Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof App 20040023449 - Hsu, Louis L. ; et al.	2004-02-05
Self-aligned, planarized thin-film transistors, devices employing the same Grant 6,649,935 - Hsu , et al. November 18, 2	2003-11-18
Intrinsic dual gate oxide mosfet using a damascene gate process App 20030109090 - Bertin, Claude Louis ; et al.	2003-06-12
Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox Grant 6,577,156 - Anand , et al. June 10, 2	2003-06-10
Intrinsic dual gate oxide MOSFET using a damascene gate process Grant 6,531,410 - Bertin , et al. March 11, 2	2003-03-11
Intrinsic dual gate oxide MOSFET using a damascene gate process App 20020119637 - Bertin, Claude Louis ; et al.	2002-08-29
Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality App 20020101723 - Bertin, Claude Louis ; et al.	2002-08-01
Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox App 20020101777 - Anand, Darren L. ; et al.	2002-08-01
Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality Grant 6,388,198 - Bertin , et al. May 14, 2	2002-05-14
Impedance control using fuses Grant 6,243,283 - Bertin , et al. June 5, 2	2001-06-05
Switched body SOI (silicon on insulator) circuits and fabrication method therefor Grant 6,239,649 - Bertin , et al. May 29, 2	2001-05-29
Impedance control using fuses Grant 6,141,245 - Bertin , et al. October 31, 2	2000-10-31