Tonello; Stefano

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tonello; Stefano.The latest application filed is for "layout for dut arrays used in semiconductor wafer testing".

Company Profile

0.4.5

Tonello; Stefano - Breganze IT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Test cells for semiconductor yield improvement Grant 7,807,480 - Stine , et al. October 5, 2	2010-10-05
Layout For Dut Arrays Used In Semiconductor Wafer Testing App 20090140762 - Hess; Christopher ; et al.	2009-06-04
Layout for DUT arrays used in semiconductor wafer testing Grant 7,489,151 - Hess , et al. February 10, 2	2009-02-10
Designing an integrated circuit to improve yield using a variant design element Grant 7,487,474 - Ciplickas , et al. February 3, 2	2009-02-03
Test Cells for semiconductor yield improvement App 20080169466 - Stine; Brian ; et al.	2008-07-17
Layout for DUT arrays used in semiconductor wafer testing App 20070075718 - Hess; Christopher ; et al.	2007-04-05
Yield improvement App 20060101355 - Ciplickas; Dennis ; et al.	2006-05-11
Low power RAM memory cell using a precharge line pulse during write operation Grant 6,380,592 - Tooher , et al. April 30, 2	2002-04-30
Low Power Ram Memory Cell Using A Precharge Line Pulse During Write Operation App 20020003244 - TOOHER, MICHAEL ; et al.	2002-01-10

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