Tomsio; Nayon

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tomsio; Nayon.The latest application filed is for "power grid and bump pattern with reduced inductance and resistance".

Company Profile

0.7.6

Tomsio; Nayon - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Intelligent delay insertion based on transition Grant 7,116,126 - Tomsio , et al. October 3, 2	2006-10-03
On-chip power-on voltage initialization Grant 7,085,176 - Levy , et al. August 1, 2	2006-08-01
Priority delay insertion circuit Grant 7,016,422 - Sharma , et al. March 21, 2	2006-03-21
Power grid and bump pattern with reduced inductance and resistance Grant 6,961,247 - Tomsio , et al. November 1, 2	2005-11-01
Stable and accurate CMOS level shifter Grant 6,788,125 - Tomsio September 7, 2	2004-09-07
Resistive vias for controlling impedance and terminating I/O signals at the package level Grant 6,737,749 - Tomsio , et al. May 18, 2	2004-05-18
Method and a system to distribute clock signals in digital circuits Grant 6,737,902 - Tomsio , et al. May 18, 2	2004-05-18
Power grid and bump pattern with reduced inductance and resistance App 20040001326 - Tomsio, Nayon ; et al.	2004-01-01
Method and a system to distribute clock signals in digital circuits App 20030214340 - Tomsio, Nayon ; et al.	2003-11-20
Resistive vias for controlling impedance and terminating I/O signals at the package level App 20030116856 - Tomsio, Nayon ; et al.	2003-06-26
Zero-skew transition detection circuit App 20030120982 - Levy, Howard L. ; et al.	2003-06-26
Intelligent delay insertion based on transition App 20030072332 - Tomsio, Nayon ; et al.	2003-04-17
Priority delay insertion circuit App 20030031194 - Sharma, Harsh D. ; et al.	2003-02-13

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