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Patent applications and USPTO patent grants for Tomoyama; Tsuyoshi.The latest application filed is for "patterning methods".
Patent | Date |
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Integrated assemblies having bitline contacts, and methods of forming integrated assemblies Grant 11,056,494 - Tomoyama July 6, 2 | 2021-07-06 |
Patterning methods Grant 11,037,800 - Tomoyama , et al. June 15, 2 | 2021-06-15 |
Patterning Methods App 20200294814 - Tomoyama; Tsuyoshi ;   et al. | 2020-09-17 |
Integrated assemblies having bitline contacts Grant 10,573,654 - Tomoyama Feb | 2020-02-25 |
Integrated Assemblies Having Bitline Contacts, and Methods of Forming Integrated Assemblies App 20200043934 - Tomoyama; Tsuyoshi | 2020-02-06 |
Integrated Assemblies Having Bitline Contacts App 20190386010 - Tomoyama; Tsuyoshi | 2019-12-19 |
Semiconductor device having shallow trench isolation structure Grant 9,741,723 - Tomoyama August 22, 2 | 2017-08-22 |
Semiconductor Device Having Shallow Trench Isolation Structure App 20160233297 - TOMOYAMA; Tsuyoshi | 2016-08-11 |
Semiconductor Device And Method Of Manufacturing The Same App 20130270677 - Tomoyama; Tsuyoshi ;   et al. | 2013-10-17 |
Semiconductor device and method of manufacturing the same App 20100258907 - Tomoyama; Tsuyoshi ;   et al. | 2010-10-14 |
Semiconductor package with bypass capacitor Grant 7,667,317 - Osanai , et al. February 23, 2 | 2010-02-23 |
Semiconductor package App 20070273021 - Osanai; Fumiyuki ;   et al. | 2007-11-29 |
Semiconductor Device Having Stacked Structure And Method Of Manufacturing The Same App 20070228580 - Shibamoto; Masanori ;   et al. | 2007-10-04 |
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