Tolchinsky; Peter G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tolchinsky; Peter G..The latest application filed is for "techniques for monolithic co-integration of silicon and iii-n semiconductor transistors".

Company Profile

5.23.29

Tolchinsky; Peter G. - Beaverton OR
- Beaverton OR US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Techniques for monolithic co-integration of silicon and III-N semiconductor transistors Grant 10,879,134 - Radosavljevic , et al. December 29, 2	2020-12-29
GaN devices on engineered silicon substrates Grant 10,692,839 - Dasgupta , et al.	2020-06-23
Silicon PMOS with gallium nitride NMOS for voltage regulation Grant 10,600,787 - Dasgupta , et al.	2020-03-24
Techniques For Monolithic Co-integration Of Silicon And Iii-n Semiconductor Transistors App 20190279908 - RADOSAVLJEVIC; MARKO ; et al.	2019-09-12
Silicon Pmos With Gallium Nitride Nmos For Voltage Regulation App 20190051650 - Dasgupta; Sansaptak ; et al.	2019-02-14
Gan Devices On Engineered Silicon Substrates App 20180145052 - DASGUPTA; Sansaptak ; et al.	2018-05-24
Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby Grant 9,711,591 - Mukherjee , et al. July 18, 2	2017-07-18
Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition Grant 9,691,843 - Cappellani , et al. June 27, 2	2017-06-27
Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition Grant 9,559,160 - Cappellani , et al. January 31, 2	2017-01-31
Common-substrate Semiconductor Devices Having Nanowires Or Semiconductor Bodies With Differing Material Orientation Or Composition App 20160133735 - CAPPELLANI; Annalisa ; et al.	2016-05-12
Stacking fault and twin blocking barrier for integrating III-V on Si Grant 08617945 -	2013-12-31
Stacking fault and twin blocking barrier for integrating III-V on Si Grant 8,617,945 - Hudait , et al. December 31, 2	2013-12-31
Common-substrate Semiconductor Devices Having Nanowires Or Semiconductor Bodies With Differing Material Orientation Or Composition App 20130320294 - Cappellani; Annalisa ; et al.	2013-12-05
High hole mobility p-channel Ge transistor structure on Si substrate Grant 8,217,383 - Hudait , et al. July 10, 2	2012-07-10
Stacking Fault And Twin Blocking Barrier For Integrating Iii-v On Si App 20120142166 - Hudait; Mantu K. ; et al.	2012-06-07
Stacking fault and twin blocking barrier for integrating III-V on Si Grant 8,143,646 - Hudait , et al. March 27, 2	2012-03-27
Dislocation removal from a group III-V film grown on a semiconductor substrate Grant 7,863,710 - Hudait , et al. January 4, 2	2011-01-04
High Hole Mobility P-channel Ge Transistor Structure On Si Substrate App 20100327261 - Hudait; Mantu K. ; et al.	2010-12-30
Buffer layers for device isolation of devices grown on silicon Grant 7,851,781 - Hudait , et al. December 14, 2	2010-12-14
High hole mobility p-channel Ge transistor structure on Si substrate Grant 7,791,063 - Hudait , et al. September 7, 2	2010-09-07
Back gate doping for SOI substrates App 20100155880 - Ban; Ibrahim ; et al.	2010-06-24
Group III-V devices with delta-doped layer under channel region App 20100148153 - Hudait; Mantu K. ; et al.	2010-06-17
Methods of forming buffer layer architecture on silicon and structures formed thereby Grant 7,687,799 - Hudait , et al. March 30, 2	2010-03-30
Methods of forming buffer layer architecture on silicon and structures formed thereby App 20090315018 - Hudait; Mantu K. ; et al.	2009-12-24
Buffer layers for device isolation of devices grown on silicon App 20090218596 - Hudait; Mantu K. ; et al.	2009-09-03
Dislocation Removal From A Group Iii-v Film Grown On A Semiconductor Substrate App 20090206324 - Hudait; Mantu K. ; et al.	2009-08-20
Dislocation-free InSb quantum well structure on Si using novel buffer architecture Grant 7,573,059 - Hudait , et al. August 11, 2	2009-08-11
Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer App 20090096025 - Tolchinsky; Peter G. ; et al.	2009-04-16
Vertical Semiconductor Wafer Carrier App 20090071918 - Ramanarayanan; Panchapakesan ; et al.	2009-03-19
High Hole Mobility P-Channel Ge Transistor Structure on Si Substrate App 20090057648 - Hudait; Mantu K. ; et al.	2009-03-05
Buffer layers for device isolation of devices grown on silicon Grant 7,494,911 - Hudait , et al. February 24, 2	2009-02-24
Transistors with increased mobility in the channel zone and method of fabrication Grant 7,491,988 - Tolchinsky , et al. February 17, 2	2009-02-17
Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer Grant 7,473,614 - Tolchinsky , et al. January 6, 2	2009-01-06
Methods of vertically stacking wafers using porous silicon Grant 7,378,331 - Shaheen , et al. May 27, 2	2008-05-27
Dislocation-free InSb quantum well structure on Si using novel buffer architecture App 20080073639 - Hudait; Mantu K. ; et al.	2008-03-27
Buffer layers for device isolation of devices grown on silicon App 20080076235 - Hudait; Mantu K. ; et al.	2008-03-27
Stacking fault and twin blocking barrier for integrating III-V on Si App 20080032478 - Hudait; Mantu K. ; et al.	2008-02-07
Depositing polar materials on non-polar semiconductor substrates App 20070238281 - Hudait; Mantu K. ; et al.	2007-10-11
Insulation layer for silicon-on-insulator wafer App 20070063279 - Tolchinsky; Peter G. ; et al.	2007-03-22
Methods of vertically stacking wafers using porous silicon App 20060138627 - Shaheen; Mohamad ; et al.	2006-06-29
Method for manufacturing a silicon-on-Insulator (SOI) wafer with an etch stop layer App 20060102988 - Tolchinsky; Peter G. ; et al.	2006-05-18
Transistors with increased mobility in the channel zone and method of fabrication App 20050285212 - Tolchinsky, Peter G. ; et al.	2005-12-29
Semiconductor wafers with non-standard crystal orientations and methods of manufacturing the same App 20050217560 - Tolchinsky, Peter G. ; et al.	2005-10-06
Method for making a semiconductor device having increased carrier mobility Grant 6,924,543 - Tolchinsky , et al. August 2, 2	2005-08-02
Method of forming silicon on insulator wafers Grant 6,911,380 - Tolchinsky , et al. June 28, 2	2005-06-28
Devices and methods employing high thermal conductivity heat dissipation substrates App 20050070048 - Tolchinsky, Peter G. ; et al.	2005-03-31
Method for making a semiconductor device having increased carrier mobility App 20040251480 - Tolchinsky, Peter G. ; et al.	2004-12-16
Method of forming silicon on insulator wafers App 20040014302 - Tolchinsky, Peter G. ; et al.	2004-01-22

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