Tobita; Yoichi
Patent Applications and Registrations
Patent applications and USPTO patent grants for Tobita; Yoichi.The latest application filed is for "semiconductor memory device having a test mode setting circuit".
- Tobita; Yoichi - Itami JP
- Tobita; Yoichi - Hyogo JP
| Patent | Date |
|---|---|
| Semiconductor memory device having a test mode setting circuit Grant RE35,645 - Tobita October 28, 1 | 1997-10-28 |
| Reference voltage generating circuit Grant 5,646,516 - Tobita July 8, 1 | 1997-07-08 |
| Semiconductor memory device including a component having improved breakdown voltage characteristics Grant 5,490,116 - Tobita , et al. February 6, 1 | 1996-02-06 |
| Constant voltage generating circuit Grant RE34,290 - Tobita June 22, 1 | 1993-06-22 |
| Interconnection layer formed on embedded dielectric and method for manufacturing the same Grant 5,041,898 - Urabe , et al. August 20, 1 | 1991-08-20 |
| Random access memory with reduced access time in reading operation and operating method thereof Grant 4,984,206 - Komatsu , et al. January 8, 1 | 1991-01-08 |
| Dynamic random access memory device and operating method therefor Grant 4,933,907 - Kumanoya , et al. June 12, 1 | 1990-06-12 |
| Constant voltage generating circuit Grant 4,670,706 - Tobita June 2, 1 | 1987-06-02 |
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