Tobben; Dirk

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tobben; Dirk.The latest application filed is for "memory for producing a memory component".

Company Profile

0.17.5

Tobben; Dirk - Munich DE
Tobben; Dirk - Munchen DE
Tobben; Dirk - Muchen DE
Tobben; Dirk - Dresden OT Langebruck DE
Tobben; Dirk - Langebrueek DE
TOBBEN, DIRK - FISHKILL NY
Tobben; Dirk - Langebrueck DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for the planarization of a semiconductor structure Grant 7,030,017 - Hollatz , et al. April 18, 2	2006-04-18
Memory for producing a memory component Grant 7,012,003 - Tobben March 14, 2	2006-03-14
Memory for producing a memory component App 20050020009 - Tobben, Dirk	2005-01-27
Integrated circuit having electrical connecting elements Grant 6,803,612 - Lehr , et al. October 12, 2	2004-10-12
Field effect transistor and fabrication method Grant 6,765,248 - Tobben , et al. July 20, 2	2004-07-20
Method for the planarization of a semiconductor structure App 20040127040 - Hollatz, Mark ; et al.	2004-07-01
Integrated circuit having electrical connecting elements App 20040057301 - Lehr, Matthias Uwe ; et al.	2004-03-25
Field effect transistor and fabrication method App 20030098478 - Tobben, Dirk ; et al.	2003-05-29
Method of forming a self-aligned antifuse link Grant 6,465,282 - Tobben , et al. October 15, 2	2002-10-15
Method for expanding trenches by an anisotropic wet etch Grant 6,426,254 - Kudelka , et al. July 30, 2	2002-07-30
Method For Expanding Trenches By An Anisotropic Wet Etch App 20010016398 - KUDELKA, STEPHAN ; et al.	2001-08-23
Self-aligned metal caps for interlevel metal connections Grant 6,261,950 - Tobben , et al. July 17, 2	2001-07-17
Semiconductor structures and manufacturing methods Grant 6,245,629 - Tobben June 12, 2	2001-06-12
Formation of controlled trench top isolation layers for vertical transistors Grant 6,177,698 - Gruening , et al. January 23, 2	2001-01-23
Prevention of photoresist poisoning from dielectric antireflective coating in semiconductor fabrication Grant 6,103,456 - Tobben , et al. August 15, 2	2000-08-15
Dual damascene process for metal layers and organic intermetal layers Grant 6,066,569 - Tobben May 23, 2	2000-05-23
Metalization system having an enhanced thermal conductivity Grant 6,046,503 - Weigand , et al. April 4, 2	2000-04-04
Dual damascene structure Grant 6,033,977 - Gutsche , et al. March 7, 2	2000-03-07
Multi-level conductive structure including low capacitance material Grant 5,977,635 - Tobben , et al. November 2, 1	1999-11-02
Method of planarizing the semiconductor structure Grant 5,963,837 - Ilg , et al. October 5, 1	1999-10-05
Planarization of a non-conformal device layer in semiconductor fabrication Grant 5,880,007 - Varian , et al. March 9, 1	1999-03-09
Method for forming metallization in semiconductor devices with a self-planarizing material Grant 5,854,126 - Tobben , et al. December 29, 1	1998-12-29

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