Tjeng; Jensen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tjeng; Jensen.The latest application filed is for "processor with memory delayed bit line precharging".

Company Profile

1.10.5

Tjeng; Jensen - San Jose CA
Tjeng; Jensen - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Providing data to registers between execution stages Grant 8,909,903 - Chen , et al. December 9, 2	2014-12-09
Processor with memory delayed bit line precharging Grant 8,526,257 - Sutardja , et al. September 3, 2	2013-09-03
Processor With Memory Delayed Bit Line Precharging App 20130044555 - Sutardja; Sehat ; et al.	2013-02-21
Processor instruction cache with dual-read modes Grant 8,295,110 - Sutardja , et al. October 23, 2	2012-10-23
Processor Instruction Cache With Dual-read Modes App 20120014196 - Sutardja; Sehat ; et al.	2012-01-19
Processor instruction cache with dual-read modes Grant 8,089,823 - Sutardja , et al. January 3, 2	2012-01-03
Variable length pipeline processor architecture Grant 8,074,056 - Chen , et al. December 6, 2	2011-12-06
Processor instruction cache with dual-read modes Grant 8,027,218 - Sutardja , et al. September 27, 2	2011-09-27
Processor Instruction Cache With Dual-read Modes App 20100329058 - Sutardja; Sehat ; et al.	2010-12-30
Processor instruction cache with dual-read modes Grant 7,787,324 - Sutardja , et al. August 31, 2	2010-08-31
Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof Grant 7,730,285 - Chen , et al. June 1, 2	2010-06-01
Processor Instruction Cache With Dual-read Modes App 20080189518 - Sutardja; Sehat ; et al.	2008-08-07
Processor Instruction Cache with Dual-Read Modes App 20080165602 - Sutardja; Sehat ; et al.	2008-07-10
Data processing system with bypass reorder buffer having non-bypassable locations and combined load/store arithmetic logic unit and processing method thereof Grant 7,096,345 - Chen , et al. August 22, 2	2006-08-22

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