Tischler; Brett A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tischler; Brett A..The latest application filed is for "memory access request arbitration".

Company Profile

0.23.5

Tischler; Brett A. - Longmont CO US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for cache-based compressed display data storage Grant 8,587,600 - Tischler , et al. November 19, 2	2013-11-19
Data block transfer to cache Grant 8,368,710 - Tischler February 5, 2	2013-02-05
Thermal throttling of peripheral components in a processing device Grant 8,304,698 - Tischler November 6, 2	2012-11-06
Delayed memory access request arbitration Grant 8,065,457 - Tischler November 22, 2	2011-11-22
System and method for rotating rasterized image data Grant 7,535,474 - Scholander , et al. May 19, 2	2009-05-19
Method of configuring a system and system therefor Grant 7,519,883 - Daugherty , et al. April 14, 2	2009-04-14
Memory access request arbitration Grant 7,426,621 - Kommrusch , et al. September 16, 2	2008-09-16
Programmable interleaving in multiple-bank memories Grant 7,398,362 - Tischler July 8, 2	2008-07-08
Memory access request arbitration App 20070136545 - Kommrusch; Steven J. ; et al.	2007-06-14
Delayed memory access request arbitration App 20070067532 - Tischler; Brett A.	2007-03-22
Apparatus and method for viewing data processor bus transactions on address pins during memory idle cycles Grant 7,143,225 - Tischler , et al. November 28, 2	2006-11-28
Bus architecture using debug packets to monitor transactions on an internal data processor bus Grant 7,107,494 - Tischler September 12, 2	2006-09-12
Apparatus and method for sending in order data and out of order data on a data bus Grant 7,043,593 - Tischler , et al. May 9, 2	2006-05-09
Apparatus and method for isochronous arbitration to schedule memory refresh requests Grant 7,020,741 - Tischler March 28, 2	2006-03-28
Precision bypass clock for high speed testing of a data processor Grant 7,007,188 - Tischler , et al. February 28, 2	2006-02-28
Hierarchical texture cache Grant 6,924,810 - Tischler August 2, 2	2005-08-02
Split transactional unidirectional bus architecture and method of operation Grant 6,912,611 - Kotlowski , et al. June 28, 2	2005-06-28
Split Transactional Unidirectional Bus Architecture And Method Of Operation App 20040225781 - Kotlowski, Kenneth James ; et al.	2004-11-11
Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation Grant 6,813,673 - Kotlowski , et al. November 2, 2	2004-11-02
Multimedia processor employing a shared CPU-graphics cache Grant 6,801,207 - Tischler , et al. October 5, 2	2004-10-05
System and method for machine specific register addressing in a split transactional unidirectional bus architecture Grant 6,785,758 - Kotlowski , et al. August 31, 2	2004-08-31
Speculative bus arbitrator and method of operation Grant 6,763,415 - Tischler July 13, 2	2004-07-13
Dynamic replacement technique in a shared cache Grant 6,591,347 - Tischler , et al. July 8, 2	2003-07-08
Hierarchical texture cache Grant 6,483,516 - Tischler November 19, 2	2002-11-19
Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation App 20020161953 - Kotlowski, Kenneth James ; et al.	2002-10-31
Dynamic Replacement Technique In A Shared Cache App 20010049771 - TISCHLER, BRETT A. ; et al.	2001-12-06

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