Ting; Jyh-Kang
Patent Applications and Registrations
Patent applications and USPTO patent grants for Ting; Jyh-Kang.The latest application filed is for "cell layout and structure".
Company Profile
3.25.22
- Ting; Jyh-Kang - Baoshan Township TW
- Ting; Jyh-Kang - Baoshan Towmship TW
- Ting; Jyh-Kang - Hsin-Chu TW
Patent Activity
| Patent | Date |
|---|---|
| Cell layout and structure Grant 11,281,835 - Hsieh , et al. March 22, 2 | 2022-03-22 |
| Conductive line patterning Grant 10,998,304 - Liu , et al. May 4, 2 | 2021-05-04 |
| Cell Layout and Structure App 20200257842 - Hsieh; Tung-Heng ; et al. | 2020-08-13 |
| Cell layout and structure Grant 10,664,639 - Hsieh , et al. | 2020-05-26 |
| Conductive Line Patterning App 20190244950 - Liu; Ru-Gun ; et al. | 2019-08-08 |
| Mask optimization for multi-layer contacts Grant 10,283,495 - Liu , et al. | 2019-05-07 |
| Conductive line patterning Grant 10,269,785 - Liu , et al. | 2019-04-23 |
| Cell Layout and Structure App 20180253522 - Hsieh; Tung-Heng ; et al. | 2018-09-06 |
| Cell layout and structure Grant 9,984,191 - Hsieh , et al. May 29, 2 | 2018-05-29 |
| Method for preventing photoresist corner rounding effects Grant 9,746,783 - Lee , et al. August 29, 2 | 2017-08-29 |
| Implant region definition Grant 9,637,818 - Wu , et al. May 2, 2 | 2017-05-02 |
| Semiconductor arrangement and formation thereof Grant 9,620,420 - Lu , et al. April 11, 2 | 2017-04-11 |
| Conductive Line Patterning App 20170025401 - Liu; Ru-Gun ; et al. | 2017-01-26 |
| Cut mask design layers to provide compact cell height Grant 9,551,923 - Wang , et al. January 24, 2 | 2017-01-24 |
| Semiconductor device having a metal gate Grant 9,508,791 - Tsai , et al. November 29, 2 | 2016-11-29 |
| Conductive line patterning Grant 9,472,501 - Liu , et al. October 18, 2 | 2016-10-18 |
| Mask Optimization For Multi-Layer Contacts App 20160293590 - Liu; Ru-Gun ; et al. | 2016-10-06 |
| Semiconductor Arrangement And Formation Thereof App 20160268170 - Lu; Chen-Hung ; et al. | 2016-09-15 |
| Mask optimization for multi-layer contacts Grant 9,391,056 - Liu , et al. July 12, 2 | 2016-07-12 |
| Semiconductor arrangement and formation thereof Grant 9,349,634 - Lu , et al. May 24, 2 | 2016-05-24 |
| Semiconductor Device Having A Metal Gate App 20160133693 - Tsai; Tsung-Chieh ; et al. | 2016-05-12 |
| Cell Layout and Structure App 20160063166 - Hsieh; Tung-Heng ; et al. | 2016-03-03 |
| Conductive Line Patterning App 20150333002 - Liu; Ru-Gun ; et al. | 2015-11-19 |
| Implant Region Definition App 20150322565 - Wu; Juing-Yi ; et al. | 2015-11-12 |
| Cut Mask Design Layers To Provide Compact Cell Height App 20150286765 - Wang; Yen-Sen ; et al. | 2015-10-08 |
| Conductive line patterning Grant 9,136,168 - Liu , et al. September 15, 2 | 2015-09-15 |
| Semiconductor Arrangement And Formation Thereof App 20150243552 - Lu; Chen-Hung ; et al. | 2015-08-27 |
| Implant region definition Grant 9,087,773 - Wu , et al. July 21, 2 | 2015-07-21 |
| Method, system and software for accessing design rules and library of design features while designing semiconductor device layout Grant 9,047,437 - Chen , et al. June 2, 2 | 2015-06-02 |
| Implant Region Definition App 20150072480 - Wu; Juing-Yi ; et al. | 2015-03-12 |
| Method For Preventing Photoresist Corner Rounding Effects App 20150050810 - Lee; Liang-Yao ; et al. | 2015-02-19 |
| Mask Optimization for Multi-Layer Contacts App 20150048457 - Liu; Ru-Gun ; et al. | 2015-02-19 |
| Conductive Line Patterning App 20150001734 - Liu; Ru-Gun ; et al. | 2015-01-01 |
| Method, System And Software For Accessing Design Rules And Library Of Design Features While Designing Semiconductor Device Layout App 20140282294 - CHEN; Chin-An ; et al. | 2014-09-18 |
| Rule coverage rate auto-extraction and rule number auto-mark Grant 8,806,417 - Chao , et al. August 12, 2 | 2014-08-12 |
| Method, system and software for accessing design rules and library of design features while designing semiconductor device layout Grant 8,769,475 - Chen , et al. July 1, 2 | 2014-07-01 |
| Method, System And Software For Accessing Design Rules And Library Of Design Features While Designing Semiconductor Device Layout App 20130111418 - Chen; Chin-An ; et al. | 2013-05-02 |
| Semiconductor Device And Fabrication Method Thereof App 20130075796 - TSAI; Tsung-Chieh ; et al. | 2013-03-28 |
| Method for designing interconnect for a new processing technology App 20070158835 - Lin; Jian-Hong ; et al. | 2007-07-12 |
| Precision capacitor array Grant 5,838,032 - Ting November 17, 1 | 1998-11-17 |
| Method of forming a tungsten silicide capacitor having a high breakdown voltage Grant 5,804,488 - Shih , et al. September 8, 1 | 1998-09-08 |
| Method of making a precision capacitor array Grant 5,635,421 - Ting June 3, 1 | 1997-06-03 |
| Method of making high precision w-polycide-to-poly capacitors in digital/analog process Grant 5,554,558 - Hsu , et al. September 10, 1 | 1996-09-10 |
| Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process Grant 5,480,828 - Hsu , et al. January 2, 1 | 1996-01-02 |
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