loadpatents
name:-0.0034840106964111
name:-0.029205083847046
name:-0.00059318542480469
Ting; Chiu H. Patent Filings

Ting; Chiu H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ting; Chiu H..The latest application filed is for "barrier enhancement process for copper interconnects".

Company Profile
0.25.2
  • Ting; Chiu H. - Saratoga CA
  • Ting; Chiu H. - Hopewell Junction NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Barrier enhancement process for copper interconnects
App 20060076244 - Ting; Chiu H. ;   et al.
2006-04-13
Barrier enhancement process for copper interconnects
App 20030010645 - Ting, Chiu H. ;   et al.
2003-01-16
Metallized interconnection structure
Grant 6,492,722 - Cheung , et al. December 10, 2
2002-12-10
Method for depositing and/or removing material on a substrate
Grant 6,365,025 - Ting , et al. April 2, 2
2002-04-02
Multiple station processing chamber and method for depositing and/or removing material on a substrate
Grant 6,187,152 - Ting , et al. February 13, 2
2001-02-13
Method and apparatus for the disposal of processing fluid used to deposit and/or remove material on a substrate
Grant 6,183,611 - Ting , et al. February 6, 2
2001-02-06
Introducing and reclaiming liquid in a wafer processing chamber
Grant 6,179,982 - Ting , et al. January 30, 2
2001-01-30
Metallized interconnection structure and method of making the same
Grant 6,153,521 - Cheung , et al. November 28, 2
2000-11-28
Rotating anode for a wafer processing chamber
Grant 6,077,412 - Ting , et al. June 20, 2
2000-06-20
Apparatus and method utilizing an electrode adapter for customized contact placement on a wafer
Grant 6,022,465 - Ting , et al. February 8, 2
2000-02-08
Process chamber and method for depositing and/or removing material on a substrate
Grant 6,017,437 - Ting , et al. January 25, 2
2000-01-25
Integrated vacuum and plating cluster system
Grant 6,017,820 - Ting , et al. January 25, 2
2000-01-25
Copper replenishment technique for precision copper plating system
Grant 5,997,712 - Ting , et al. December 7, 1
1999-12-07
Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications
Grant 5,891,513 - Dubin , et al. April 6, 1
1999-04-06
Sealed semiconductor chip and process for fabricating sealed semiconductor chip
Grant 5,856,705 - Ting January 5, 1
1999-01-05
Electroless deposition equipment or apparatus and method of performing electroless deposition
Grant 5,830,805 - Shacham-Diamand , et al. November 3, 1
1998-11-03
Protected encapsulation of catalytic layer for electroless copper interconnect
Grant 5,824,599 - Schacham-Diamand , et al. October 20, 1
1998-10-20
Sealed semiconductor chip
Grant 5,742,094 - Ting April 21, 1
1998-04-21
Use of cobalt tungsten phosphide as a barrier material for copper metallization
Grant 5,695,810 - Dubin , et al. December 9, 1
1997-12-09
Selective electroless copper deposited interconnect plugs for ULSI applications
Grant 5,674,787 - Zhao , et al. October 7, 1
1997-10-07
Process for fabricating sealed semiconductor chip using silicon nitride passivation film
Grant 5,300,461 - Ting April 5, 1
1994-04-05
Fully planar metalization process
Grant 5,183,795 - Ting , et al. February 2, 1
1993-02-02
Electroless deposition for IC fabrication
Grant 5,169,680 - Ting , et al. December 8, 1
1992-12-08
Chemical modification of spin-on glass for improved performance in IC fabrication
Grant 4,885,262 - Ting , et al. December 5, 1
1989-12-05
Process for forming MOS transistor with buried oxide regions for insulation
Grant 4,700,454 - Baerg , et al. October 20, 1
1987-10-20
Process for forming isolated silicon regions and field-effect devices on a silicon substrate
Grant 4,654,958 - Baerg , et al. April 7, 1
1987-04-07
High sensitivity positive resist layers and mask formation process
Grant 3,934,057 - Moreau , et al. January 20, 1
1976-01-20

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