| Patent | Date |
|---|
Active Zones With Offset In Semiconductor Cell
App 20220310584 - WU; Guo-Huei ; et al. | 2022-09-29 |
Semiconductor Device Having Buried Logic Conductor Type Of Complementary Field Effect Transistor, Method Of Forming Same
App 20220310598 - Wu; Guo-Huei ; et al. | 2022-09-29 |
Integrated Circuit
App 20220302111 - WU; Guo-Huei ; et al. | 2022-09-22 |
Semiconductor Structure And Method For Manufacturing The Same
App 20220293638 - WANG; POCHUN ; et al. | 2022-09-15 |
Multi-bit structure
Grant 11,444,071 - Chien , et al. September 13, 2 | 2022-09-13 |
Integrated circuit having a high cell density
Grant 11,437,319 - Chen , et al. September 6, 2 | 2022-09-06 |
Integrated Circuit Device
App 20220271025 - CHEN; Chien-Ying ; et al. | 2022-08-25 |
Semiconductor device and manufacturing method thereof
Grant 11,417,601 - Wang , et al. August 16, 2 | 2022-08-16 |
Semiconductor structure and layout method of a semiconductor structure
Grant 11,417,588 - Chen , et al. August 16, 2 | 2022-08-16 |
Integrated circuit and method of manufacturing same
Grant 11,409,938 - Chiang , et al. August 9, 2 | 2022-08-09 |
Integrated Circuit Layouts With Source And Drain Contacts Of Different Widths
App 20220208976 - CIOU; Shang-Syuan ; et al. | 2022-06-30 |
Integrated circuit
Grant 11,374,003 - Wu , et al. June 28, 2 | 2022-06-28 |
Transmission Gate Manufacturing Method
App 20220188501 - CHIEN; Shao-Lun ; et al. | 2022-06-16 |
Semiconductor structure and method for manufacturing the same
Grant 11,362,110 - Wang , et al. June 14, 2 | 2022-06-14 |
Semiconductor device having buried logic conductor type of complementary field effect transistor, method of generating layout diagram and system for same
Grant 11,362,090 - Wu , et al. June 14, 2 | 2022-06-14 |
Integrated circuit layout method, device, and system
Grant 11,355,488 - Chen , et al. June 7, 2 | 2022-06-07 |
Engineering Change Order Cell Structure Having Always-on Transistor
App 20220164518 - CHEN; Shun Li ; et al. | 2022-05-26 |
Integrated Circuit And Manufacturing Method Thereof
App 20220157804 - WANG; Xin-Yong ; et al. | 2022-05-19 |
Semiconductor Device And Methods Of Manufacturing Same
App 20220130760 - WU; Guo-Huei ; et al. | 2022-04-28 |
Cell structure with intermediate metal layers for power supplies
Grant 11,315,874 - Tien , et al. April 26, 2 | 2022-04-26 |
Reduced Area Standard Cell Abutment Configurations
App 20220114322 - LU; Chi-Yu ; et al. | 2022-04-14 |
Integrated circuit layouts with source and drain contacts of different widths
Grant 11,302,787 - Ciou , et al. April 12, 2 | 2022-04-12 |
Transmission gate structure and method
Grant 11,295,055 - Chien , et al. April 5, 2 | 2022-04-05 |
Integrated Circuit
App 20220093646 - WU; Guo-Huei ; et al. | 2022-03-24 |
Cell Structure With Intermediate Metal Layers For Power Supplies
App 20220084945 - Tien; Li-Chun ; et al. | 2022-03-17 |
Power Gating Cell Structure
App 20220085005 - Chang; Wei-Ling ; et al. | 2022-03-17 |
Engineering change order cell structure having always-on transistor
Grant 11,275,885 - Chen , et al. March 15, 2 | 2022-03-15 |
Interconnect Structure In Semiconductor Device And Method Of Forming The Same
App 20220077059 - WU; GUO-HUEI ; et al. | 2022-03-10 |
Method For Generating A Layout Diagram Of A Semiconductor Device Including Power-grid-adapted Route-spacing
App 20220075923 - TIEN; Li-Chun ; et al. | 2022-03-10 |
Integrated Circuit and Layout Method for Standard Cell Structures
App 20220058330 - CHEN; Sheng-Hsiung ; et al. | 2022-02-24 |
Semiconductor Structure And Layout Method Of A Semiconductor Structure
App 20220037233 - CHEN; WEI-REN ; et al. | 2022-02-03 |
Integrated circuit layout and method of configuring the same
Grant 11,239,228 - Lin , et al. February 1, 2 | 2022-02-01 |
Connection structure for stacked substrates
Grant 11,217,553 - Tseng , et al. January 4, 2 | 2022-01-04 |
Reduced area standard cell abutment configurations
Grant 11,216,608 - Lu , et al. January 4, 2 | 2022-01-04 |
Multi-bit Structure
App 20210407986 - CHIEN; Shao-Lun ; et al. | 2021-12-30 |
Integrated Circuit Device And Method
App 20210407985 - CHEN; Chih-Liang ; et al. | 2021-12-30 |
Integrated Circuit
App 20210384187 - LI; Jian-Sing ; et al. | 2021-12-09 |
Method Of Forming Semiconductor Device Including Deep Vias
App 20210384121 - GUO; Ta-Pen ; et al. | 2021-12-09 |
Semiconductor Device And Manufacturing Method Thereof
App 20210384128 - WANG; Xin-Yong ; et al. | 2021-12-09 |
Integrated Circuit Structure
App 20210374323 - ZHUANG; Hui-Zhong ; et al. | 2021-12-02 |
Semiconductor device including power-grid-adapted route-spacing and method for generating layout diagram of same
Grant 11,182,529 - Tien , et al. November 23, 2 | 2021-11-23 |
Integrated Circuit, System And Method Of Forming The Same
App 20210358848 - WU; Guo-Huei ; et al. | 2021-11-18 |
Semiconductor Device Including Buried Conductive Fingers And Method Of Making The Same
App 20210358847 - CHEN; Chih-Liang ; et al. | 2021-11-18 |
Odd-fin height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same
Grant 11,177,256 - Zhuang , et al. November 16, 2 | 2021-11-16 |
Integrated circuit and layout method for standard cell structures
Grant 11,170,152 - Chen , et al. November 9, 2 | 2021-11-09 |
Integrated Circuit And Method For Forming The Same
App 20210343646 - CHEN; Chih-Liang ; et al. | 2021-11-04 |
Semiconductor Device And Layout Design Thereof
App 20210343636 - Lin; Chung-Te ; et al. | 2021-11-04 |
Integrated Circuit Fin Layout Method
App 20210342514 - HUANG; Po-Hsiang ; et al. | 2021-11-04 |
Integrated Circuit With Constrained Metal Line Arrangement
App 20210294961 - WANG; XinYong ; et al. | 2021-09-23 |
Method For Manufacturing A Cell Having Pins And Semiconductor Device Based On Same
App 20210294957 - SUE; Pin-Dai ; et al. | 2021-09-23 |
Semiconductor device including deep vias, and method of generating layout diagram for same
Grant 11,127,673 - Guo , et al. September 21, 2 | 2021-09-21 |
Double Height Cell Regions, Semiconductor Device Having The Same, And Method Of Generating A Layout Diagram Corresponding To The Same
App 20210288144 - YANG; Jung-Chan ; et al. | 2021-09-16 |
Method For Manufacturing Standard Cell Regions And Engineering Change Order (eco) Cell Regions
App 20210286928 - TIEN; Li-Chun ; et al. | 2021-09-16 |
Semiconductor Structure
App 20210280608 - CHOU; HSUEH-CHIH ; et al. | 2021-09-09 |
Integrated Circuit Having Angled Conductive Feature
App 20210280572 - HSIEH; Tung-Heng ; et al. | 2021-09-09 |
Integrated circuit
Grant 11,107,805 - Li , et al. August 31, 2 | 2021-08-31 |
Semiconductor Device Including Standard Cells
App 20210257388 - GUO; Ta-Pen ; et al. | 2021-08-19 |
Semiconductor device and layout design thereof
Grant 11,088,067 - Lin , et al. August 10, 2 | 2021-08-10 |
Metal Cut Region Location System
App 20210240903 - YANG; Jung-Chan ; et al. | 2021-08-05 |
Semiconductor Device Having Buried Logic Conductor Type Of Complementary Field Effect Transistor, Method Of Generating Layout Diagram And System For Same
App 20210242205 - WU; Guo-Huei ; et al. | 2021-08-05 |
Integrated circuit fin layout method, system, and structure
Grant 11,080,453 - Huang , et al. August 3, 2 | 2021-08-03 |
Integrated circuit layout with asymmetric metal lines
Grant 11,081,479 - Tsai , et al. August 3, 2 | 2021-08-03 |
Semiconductor device including a conductive feature over an active region
Grant 11,075,164 - Hsieh , et al. July 27, 2 | 2021-07-27 |
Method And System For Generating Layout Diagram For Semiconductor Device Having Engineering Change Order (eco) Cells
App 20210224444 - CHIU; Mao-Wei ; et al. | 2021-07-22 |
Integrated Circuit Layout Method And System
App 20210209284 - LI; Jian-Sing ; et al. | 2021-07-08 |
Semiconductor structure
Grant 11,037,957 - Chou , et al. June 15, 2 | 2021-06-15 |
Semiconductor device including a conductive feature over an active region
Grant 11,031,334 - Hsieh , et al. June 8, 2 | 2021-06-08 |
Integrated circuit with constrained metal line arrangement
Grant 11,030,382 - Wang , et al. June 8, 2 | 2021-06-08 |
Method for generating layout diagram including cell having pin patterns and semiconductor device based on same
Grant 11,030,372 - Sue , et al. June 8, 2 | 2021-06-08 |
System for generating standard cell layout having engineering change order (ECO) cells
Grant 11,030,373 - Tien , et al. June 8, 2 | 2021-06-08 |
Integrated circuit having angled conductive feature
Grant 11,024,622 - Hsieh , et al. June 1, 2 | 2021-06-01 |
Semiconductor device including standard cells
Grant 11,011,545 - Guo , et al. May 18, 2 | 2021-05-18 |
Metal cut region location method and system
Grant 10,997,348 - Yang , et al. May 4, 2 | 2021-05-04 |
Semiconductor device including standard cells having different cell height
Grant 10,998,340 - Guo , et al. May 4, 2 | 2021-05-04 |
Integrated Circuit And Method Of Manufacturing Same
App 20210124866 - CHIANG; Ting-Wei ; et al. | 2021-04-29 |
Integrated Circuit With Constrained Metal Line Arrangement
App 20210110000 - WANG; XinYong ; et al. | 2021-04-15 |
Integrated circuit layout method, device, and system
Grant 10,970,451 - Li , et al. April 6, 2 | 2021-04-06 |
Method and system for generating layout diagram for semiconductor device having engineering change order (ECO) cells
Grant 10,970,440 - Chiu , et al. April 6, 2 | 2021-04-06 |
Double height cell regions, semiconductor device having the same, and method of generating a layout diagram corresponding to the same
Grant 10,971,586 - Yang , et al. April 6, 2 | 2021-04-06 |
Semiconductor Structure And Method For Manufacturing The Same
App 20210098500 - WANG; POCHUN ; et al. | 2021-04-01 |
Double Rule Integrated Circuit Layouts For A Dual Transmission Gate
App 20210098453 - PENG; Shih-Wei ; et al. | 2021-04-01 |
Integrated Circuit And Method Of Forming An Integrated Circuit
App 20210097225 - ZHUANG; Hui-Zhong ; et al. | 2021-04-01 |
Transmission Gate Structure And Method
App 20210089702 - CHIEN; Shao-Lun ; et al. | 2021-03-25 |
Integrated circuit and method of fabricating the same
Grant 10,950,594 - Lin , et al. March 16, 2 | 2021-03-16 |
Engineering Change Order Cell Structure Having Always-on Transistor
App 20210056249 - CHEN; Shun Li ; et al. | 2021-02-25 |
Integrated Circuit Having a High Cell Density
App 20210028108 - Chen; Sheng-Hsiung ; et al. | 2021-01-28 |
Integrated circuit and method of manufacturing same
Grant 10,885,254 - Chiang , et al. January 5, 2 | 2021-01-05 |
Double rule integrated circuit layouts for a dual transmission gate
Grant 10,868,008 - Peng , et al. December 15, 2 | 2020-12-15 |
Transmission gate structure, layout, methods, and system
Grant 10,867,113 - Chien , et al. December 15, 2 | 2020-12-15 |
Integrated circuit and method of forming an integrated circuit
Grant 10,867,114 - Zhuang , et al. December 15, 2 | 2020-12-15 |
Engineering change order cell structure having always-on transistor
Grant 10,846,458 - Chen , et al. November 24, 2 | 2020-11-24 |
Integrated Circuit Layout Method, Device, And System
App 20200350307 - CHEN; Chien-Ying ; et al. | 2020-11-05 |
Integrated Circuit Layout and Method of Configuring the Same
App 20200335489 - Lin; Chung-Te ; et al. | 2020-10-22 |
Integrated Circuit And Layout Method For Standard Cell Structures
App 20200327274 - CHEN; Sheng-Hsiung ; et al. | 2020-10-15 |
Integrated Circuit
App 20200328201 - LI; Jian-Sing ; et al. | 2020-10-15 |
Integrated Circuit
App 20200328210 - WU; Guo-Huei ; et al. | 2020-10-15 |
Semiconductor Device and Layout Design Thereof
App 20200328148 - Lin; Chung-Te ; et al. | 2020-10-15 |
Integrated circuit having a high cell density
Grant 10,804,200 - Chen , et al. October 13, 2 | 2020-10-13 |
Integrated Circuit, System For And Method Of Forming An Integrated Circuit
App 20200320244 - YANG; Jung-Chan ; et al. | 2020-10-08 |
Method and system for pin layout
Grant 10,796,060 - Chang , et al. October 6, 2 | 2020-10-06 |
Cell Of Transmission Gate Free Circuit And Integrated Circuit Layout Including The Same
App 20200313659 - GUO; Ta-Pen ; et al. | 2020-10-01 |
Method And System For Generating Layout Diagram For Semiconductor Device Having Engineering Change Order (eco) Cells
App 20200302101 - CHIU; Mao-Wei ; et al. | 2020-09-24 |
Semiconductor Structure
App 20200286919 - CHOU; HSUEH-CHIH ; et al. | 2020-09-10 |
Integrated circuit layout method and device
Grant 10,741,540 - Chen , et al. A | 2020-08-11 |
Integrated circuit, system for and method of forming an integrated circuit
Grant 10,740,531 - Yang , et al. A | 2020-08-11 |
Integrated circuit and layout method for standard cell structures
Grant 10,733,352 - Chen , et al. | 2020-08-04 |
Semiconductor device and layout design thereof
Grant 10,727,177 - Lin , et al. | 2020-07-28 |
Integrated circuit layout and method of configuring the same
Grant 10,707,199 - Lin , et al. | 2020-07-07 |
Cell of transmission gate free circuit and integrated circuit layout including the same
Grant 10,686,428 - Guo , et al. | 2020-06-16 |
Semiconductor structure
Grant 10,685,982 - Chou , et al. | 2020-06-16 |
System For Generating Standard Cell Layout Having Engineering Change Order (eco) Cells
App 20200184138 - TIEN; Li-Chun ; et al. | 2020-06-11 |
Semiconductor device having engineering change order (ECO) cells
Grant 10,678,977 - Chiu , et al. | 2020-06-09 |
Integrated Circuit Fin Layout Method, System, And Structure
App 20200134122 - HUANG; Po-Hsiang ; et al. | 2020-04-30 |
Double Rule Integrated Circuit Layouts For A Dual Transmission Gate
App 20200135732 - PENG; Shih-Wei ; et al. | 2020-04-30 |
Reduced Area Standard Cell Abutment Configurations
App 20200134126 - LU; Chi-Yu ; et al. | 2020-04-30 |
Method For Generating Layout Diagram Including Cell Having Pin Patterns And Semiconductor Device Based On Same
App 20200134124 - SUE; Pin-Dai ; et al. | 2020-04-30 |
Integrated Circuit Layouts With Source And Drain Contacts Of Different Widths
App 20200135869 - Ciou; Shang-Syuan ; et al. | 2020-04-30 |
Integrated Circuits And Manufacturing Methods Thereof
App 20200126986 - KESHAVARZI; Ali ; et al. | 2020-04-23 |
Integrated Circuit Having Angled Conductive Feature
App 20200126966 - HSIEH; Tung-Heng ; et al. | 2020-04-23 |
Semiconductor Device Including Standard Cells
App 20200119048 - GUO; Ta-Pen ; et al. | 2020-04-16 |
Integrated Circuit Layout Method, Device, And System
App 20200104446 - LI; Jian-Sing ; et al. | 2020-04-02 |
Metal Cut Region Location Method And System
App 20200104448 - YANG; Jung-Chan ; et al. | 2020-04-02 |
Transmission Gate Structure, Layout, Methods, And System
App 20200082052 - CHIEN; Shao-Lun ; et al. | 2020-03-12 |
Engineering Change Order Cell Structure Having Always-on Transistor
App 20200074041 - CHEN; Shun Li ; et al. | 2020-03-05 |
Semiconductor Device including a Conductive Feature Over an Active Region
App 20200075476 - Hsieh; Tung-Heng ; et al. | 2020-03-05 |
Semiconductor Device Including Deep Vias, And Method Of Generating Layout Diagram For Same
App 20200058586 - GUO; Tai-Pen ; et al. | 2020-02-20 |
Semiconductor device having engineering change order (ECO) cells
Grant 10,565,345 - Tien , et al. Feb | 2020-02-18 |
Semiconductor device having engineering change order (ECO) cells and method of using
Grant 10,553,575 - Tien , et al. Fe | 2020-02-04 |
Integrated Circuit And Method Of Forming An Integrated Circuit
App 20200034512 - ZHUANG; Hui-Zhong ; et al. | 2020-01-30 |
Connection Structure For Stacked Substrates
App 20200027853 - Tseng; Hsiang-Jen ; et al. | 2020-01-23 |
Connecting Techniques For Stacked Substrates
App 20200027854 - Tseng; Hsiang-Jen ; et al. | 2020-01-23 |
Integrated circuits and manufacturing methods thereof
Grant 10,535,655 - Keshavarzi , et al. Ja | 2020-01-14 |
Double Height Cell Regions, Semiconductor Device Having The Same, And Method Of Generating A Layout Diagram Corresponding To The
App 20200006481 - YANG; Jung-Chan ; et al. | 2020-01-02 |
Semiconductor Device Including a Conductive Feature Over an Active Region
App 20200006217 - Hsieh; Tung-Heng ; et al. | 2020-01-02 |
Odd-fin Height Cell Regions, Semiconductor Device Having The Same, And Method Of Generating A Layout Diagram Corresponding To Th
App 20200006335 - ZHUANG; Hui-Zhong ; et al. | 2020-01-02 |
Integrated Circuit Layout Method, Device, And System
App 20200006316 - CHEN; Chien-Ying ; et al. | 2020-01-02 |
Double Rule Integrated Circuit Layouts For A Dual Transmission Gate
App 20200006338 - PENG; Shih-Wei ; et al. | 2020-01-02 |
System and method of processing cutting layout and example switching circuit
Grant 10,522,527 - Hsieh , et al. Dec | 2019-12-31 |
Double rule integrated circuit layouts for a dual transmission gate
Grant 10,522,542 - Peng , et al. Dec | 2019-12-31 |
Semiconductor device including a conductive feature over an active region
Grant 10,504,837 - Hsieh , et al. Dec | 2019-12-10 |
Connecting techniques for stacked CMOS devices
Grant 10,497,661 - Tseng , et al. De | 2019-12-03 |
Semiconductor Device Including Power-grid-adapted Route-spacing And Method For Generating Layout Diagram Of Same
App 20190303527 - TIEN; Li-Chun ; et al. | 2019-10-03 |
Integrated Circuit and Method of Fabricating the Same
App 20190279975 - Lin; Chung-Te ; et al. | 2019-09-12 |
Integrated Circuit And Method Of Manufacturing Same
App 20190251225 - CHIANG; Ting-Wei ; et al. | 2019-08-15 |
Integrated Circuit Layout and Method of Configuring the Same
App 20190252367 - Lin; Chung-Te ; et al. | 2019-08-15 |
Integrated circuit and method of forming an integrated circuit
Grant 10,380,315 - Zhuang , et al. A | 2019-08-13 |
Method And System For Pin Layout
App 20190243940 - CHANG; FONG-YUAN ; et al. | 2019-08-08 |
Method of generating engineering change order (ECO) layout of base cell and computer-readable medium comprising executable instructions for carrying out said method
Grant 10,339,250 - Tien , et al. | 2019-07-02 |
Integrated circuit and method of fabricating the same
Grant 10,325,900 - Lin , et al. | 2019-06-18 |
Cell Of Transmission Gate Free Circuit And Integrated Circuit Layout Including The Same
App 20190173456 - GUO; Ta-Pen ; et al. | 2019-06-06 |
Semiconductor Structure
App 20190164992 - CHOU; HSUEH-CHIH ; et al. | 2019-05-30 |
Integrated Circuit And Layout Method For Standard Cell Structures
App 20190155984 - CHEN; Sheng-Hsiung ; et al. | 2019-05-23 |
Integrated circuit and method of manufacturing same
Grant 10,296,694 - Chiang , et al. | 2019-05-21 |
Semiconductor Device Having Engineering Change Order (eco) Cells
App 20190147132 - CHIU; Mao-Wei ; et al. | 2019-05-16 |
Semiconductor Device Including Standard Cells
App 20190148407 - GUO; Ta-Pen ; et al. | 2019-05-16 |
Semiconductor device layout
Grant 10,277,227 - Sue , et al. | 2019-04-30 |
Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same
Grant 10,270,430 - Guo , et al. | 2019-04-23 |
Integrated circuit layout and method of configuring the same
Grant 10,269,784 - Lin , et al. | 2019-04-23 |
Method and system for pin layout
Grant 10,268,796 - Chang , et al. | 2019-04-23 |
Standard Cell Layout, Semiconductor Device Having Engineering Change Order (eco) Cells And Method
App 20190114382 - TIEN; Li-Chun ; et al. | 2019-04-18 |
Integrated Circuit, System For And Method Of Forming An Integrated Circuit
App 20190102503 - YANG; Jung-Chan ; et al. | 2019-04-04 |
Integrated Circuit Having a High Cell Density
App 20190096805 - Chen; Sheng-Hsiung ; et al. | 2019-03-28 |
Semiconductor Device and Layout Design Thereof
App 20190067185 - Lin; Chung-Te ; et al. | 2019-02-28 |
Integrated circuit and method of fabricating the same
Grant 10,163,880 - Lin , et al. Dec | 2018-12-25 |
Circuits and structures including tap cells and fabrication methods thereof
Grant 10,157,910 - Xu , et al. Dec | 2018-12-18 |
Integrated circuit having a high cell density
Grant 10,157,840 - Chen , et al. Dec | 2018-12-18 |
Semiconductor devices with cells comprising routing resources
Grant 10,157,902 - Chiu , et al. Dec | 2018-12-18 |
Semiconductor device and layout design thereof
Grant 10,141,256 - Lin , et al. Nov | 2018-11-27 |
Integrated Circuit and Method of Fabricating the Same
App 20180337167 - Lin; Chung-Te ; et al. | 2018-11-22 |
Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
Grant 10,127,340 - Chiu , et al. November 13, 2 | 2018-11-13 |
Cell Of Transmission Gate Free Circuit And Integrated Circuit Layout Including The Same
App 20180183414 - GUO; Ta-Pen ; et al. | 2018-06-28 |
Gate pad layout patterns for masks and structures
Grant 10,007,750 - Chiang , et al. June 26, 2 | 2018-06-26 |
Integrated Circuit Having a High Cell Density
App 20180158776 - Chen; Sheng-Hsiung ; et al. | 2018-06-07 |
Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device
Grant 9,991,158 - Hsieh , et al. June 5, 2 | 2018-06-05 |
Integrated Circuit, System For And Method Of Forming An Integrated Circuit
App 20180150589 - YANG; Jung-Chan ; et al. | 2018-05-31 |
Standard Cell Layout, Semiconductor Device Having Engineering Change Order (eco) Cells And Method
App 20180150586 - TIEN; Li-Chun ; et al. | 2018-05-31 |
Connecting Techniques For Stacked Cmos Devices
App 20180108635 - Tseng; Hsiang-Jen ; et al. | 2018-04-19 |
Standard Cell Layout, Semiconductor Device Having Engineering Change Order (eco) Cells And Method
App 20180096981 - CHIU; Mao-Wei ; et al. | 2018-04-05 |
Method And System For Pin Layout
App 20180075181 - CHANG; FONG-YUAN ; et al. | 2018-03-15 |
Semiconductor Device Having Engineering Change Order (eco) Cells And Method Of Using
App 20180076190 - TIEN; Li-Chun ; et al. | 2018-03-15 |
Integrated Circuit And Method Of Forming An Integrated Circuit
App 20180075182 - ZHUANG; Hui-Zhong ; et al. | 2018-03-15 |
Method of forming layout design
Grant 9,899,263 - Hsieh , et al. February 20, 2 | 2018-02-20 |
Integrated Circuit And Method Of Manufacturing Same
App 20180004884 - CHIANG; Ting-Wei ; et al. | 2018-01-04 |
Integrated Circuit Layout And Method Of Configuring The Same
App 20180006009 - LIN; Chung-Te ; et al. | 2018-01-04 |
Connecting techniques for stacked CMOS devices
Grant 9,853,008 - Tseng , et al. December 26, 2 | 2017-12-26 |
Cell grid architecture for FinFET technology
Grant 9,846,757 - Zhuang , et al. December 19, 2 | 2017-12-19 |
Method for cell placement in semiconductor layout and system thereof
Grant 9,846,755 - Kuo , et al. December 19, 2 | 2017-12-19 |
Semiconductor Devices With Cells Comprising Routing Resources
App 20170345810 - CHIU; MAO-WEI ; et al. | 2017-11-30 |
Semiconductor Device Layout
App 20170346490 - Sue; Pin-Dai ; et al. | 2017-11-30 |
Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
Grant 9,831,230 - Tien , et al. November 28, 2 | 2017-11-28 |
Integrated Circuit And Method Of Fabricating The Same
App 20170323877 - LIN; Chung-Te ; et al. | 2017-11-09 |
Integrated circuit with elongated coupling
Grant 9,806,071 - Hsieh , et al. October 31, 2 | 2017-10-31 |
Semiconductor Device And Layout Design Thereof
App 20170309562 - LIN; Chung-Te ; et al. | 2017-10-26 |
System and method of layout design for integrated circuits
Grant 9,767,243 - Chiang , et al. September 19, 2 | 2017-09-19 |
Gate Pad Layout Patterns For Masks And Structures
App 20170262566 - CHIANG; Ting-Wei ; et al. | 2017-09-14 |
Methods for double-patterning-compliant standard cell design
Grant 9,747,402 - Chen , et al. August 29, 2 | 2017-08-29 |
Circuits and Structures Including Tap Cells and Fabrication Methods Thereof
App 20170194319 - XU; JIN-WEI ; et al. | 2017-07-06 |
Masks based on gate pad layout patterns of standard cell having different gate pad pitches
Grant 9,690,892 - Chiang , et al. June 27, 2 | 2017-06-27 |
Semiconductor device and layout method thereof
Grant 9,691,750 - Chou , et al. June 27, 2 | 2017-06-27 |
Layout architecture for performance improvement
Grant 9,691,666 - Lu , et al. June 27, 2 | 2017-06-27 |
Method and layout of an integrated circuit
Grant 9,653,393 - Chen , et al. May 16, 2 | 2017-05-16 |
Method and system of forming layout design
Grant 9,626,472 - Chiang , et al. April 18, 2 | 2017-04-18 |
Voltage level shifter with single well voltage
Grant 9,608,604 - Lu , et al. March 28, 2 | 2017-03-28 |
Method for checking and fixing double-patterning layout
Grant 9,594,866 - Wang , et al. March 14, 2 | 2017-03-14 |
Cell Grid Architecture For Finfet Technology
App 20170061056 - ZHUANG; Hui-Zhong ; et al. | 2017-03-02 |
Cell boundaries for self aligned multiple patterning abutments
Grant 9,563,731 - Hsu , et al. February 7, 2 | 2017-02-07 |
Non-hierarchical metal layers for integrated circuits
Grant 9,543,193 - Lu , et al. January 10, 2 | 2017-01-10 |
Method and system of layout placement based on multilayer gridlines
Grant 9,536,032 - Chiang , et al. January 3, 2 | 2017-01-03 |
Integrated circuit layout
Grant 9,529,955 - Chern , et al. December 27, 2 | 2016-12-27 |
Integrated Circuits And Manufacturing Methods Thereof
App 20160372469 - Keshavarzi; Ali ; et al. | 2016-12-22 |
Integrated Circuit with Elongated Coupling
App 20160358902 - Hsieh; Tung-Heng ; et al. | 2016-12-08 |
System And Method Of Processing Cutting Layout And Example Switching Circuit
App 20160351555 - HSIEH; Tung-Heng ; et al. | 2016-12-01 |
Semiconductor Device and Method of Manufacturing Semiconductor Device
App 20160343656 - Hsieh; Tung-Heng ; et al. | 2016-11-24 |
Connecting Techniques For Stacked Cmos Devices
App 20160336289 - Tseng; Hsiang-Jen ; et al. | 2016-11-17 |
Integrated circuit with multiple cells having different heights
Grant 9,478,609 - Chiang , et al. October 25, 2 | 2016-10-25 |
Adaptive fin design for FinFETs
Grant 9,478,540 - Ou , et al. October 25, 2 | 2016-10-25 |
Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration
Grant 9,478,533 - Ma , et al. October 25, 2 | 2016-10-25 |
Method For Cell Placement In Semiconductor Layout And System Thereof
App 20160306911 - KUO; MING-ZHANG ; et al. | 2016-10-20 |
Connecting techniques for stacked CMOS devices
Grant 9,443,758 - Tseng , et al. September 13, 2 | 2016-09-13 |
Layout Architecture for Performance Improvement
App 20160254194 - Lu; Lee-Chung ; et al. | 2016-09-01 |
Method of Forming Layout Design
App 20160254190 - Hsieh; Tung-Heng ; et al. | 2016-09-01 |
System and method of processing cutting layout and example switching circuit
Grant 9,431,381 - Hsieh , et al. August 30, 2 | 2016-08-30 |
Integrated circuit with elongated coupling
Grant 9,425,141 - Hsieh , et al. August 23, 2 | 2016-08-23 |
Distributed metal routing
Grant 9,425,095 - Xiao , et al. August 23, 2 | 2016-08-23 |
Semiconductor device and method of manufacturing semiconductor device
Grant 9,412,700 - Hsieh , et al. August 9, 2 | 2016-08-09 |
Semiconductor Device And Layout Method Thereof
App 20160225752 - CHOU; TING-WEI ; et al. | 2016-08-04 |
Adding decoupling function for TAP cells
Grant 9,406,815 - Chen , et al. August 2, 2 | 2016-08-02 |
Fuse structure
Grant 9,401,258 - Hung , et al. July 26, 2 | 2016-07-26 |
Method And System Of Forming Layout Design
App 20160147926 - CHIANG; Ting-Wei ; et al. | 2016-05-26 |
Method And System Of Forming Layout Design
App 20160147927 - CHIANG; Ting-Wei ; et al. | 2016-05-26 |
Layout architecture for performance improvement
Grant 9,337,290 - Lu , et al. May 10, 2 | 2016-05-10 |
Method of forming layout design
Grant 9,336,348 - Hsieh , et al. May 10, 2 | 2016-05-10 |
Method and layout of an integrated circuit
Grant 9,323,881 - Tseng , et al. April 26, 2 | 2016-04-26 |
Semiconductor Device And Method Of Manufacturing Semiconductor Device
App 20160111370 - HSIEH; Tung-Heng ; et al. | 2016-04-21 |
Masks formed based on integrated circuit layout design having cell that includes extended active region
Grant 9,317,646 - Lu , et al. April 19, 2 | 2016-04-19 |
Integrated Circuit With Elongated Coupling
App 20160104674 - HSIEH; Tung-Heng ; et al. | 2016-04-14 |
Integrated circuits and manufacturing methods thereof
Grant 9,312,260 - Keshavarzi , et al. April 12, 2 | 2016-04-12 |
System And Method Of Processing Cutting Layout And Example Switching Circuit
App 20160093603 - HSIEH; Tung-Heng ; et al. | 2016-03-31 |
Method Of Forming Layout Design
App 20160078164 - HSIEH; Tung-Heng ; et al. | 2016-03-17 |
Semiconductor Device, Layout Of Semiconductor Device, And Method Of Manufacturing Semiconductor Device
App 20160079162 - HSIEH; Tung-Heng ; et al. | 2016-03-17 |
Memory cell array
Grant 9,287,276 - Chang , et al. March 15, 2 | 2016-03-15 |
Fuse Structure
App 20160035527 - HUNG; Chen-Ming ; et al. | 2016-02-04 |
Method and layout of an integrated circuit
Grant 9,245,887 - Chiang , et al. January 26, 2 | 2016-01-26 |
Integrated Circuit With Multiple Cells Having Different Heights
App 20160013271 - CHIANG; Ting-Wei ; et al. | 2016-01-14 |
Gate Pad Layout Patterns Of Standard Cell Having Different Gate Pad Pitches
App 20160012169 - CHIANG; Ting-Wei ; et al. | 2016-01-14 |
Non-Hierarchical Metal Layers for Integrated Circuits
App 20150364359 - Lu; Lee-Chung ; et al. | 2015-12-17 |
Multiple via connections using connectivity rings
Grant 9,213,795 - Hsu , et al. December 15, 2 | 2015-12-15 |
Masks Formed Based On Integrated Circuit Layout Design Having Cell That Includes Extended Active Region
App 20150356225 - LU; Lee-Chung ; et al. | 2015-12-10 |
System And Method Of Layout Design For Integrated Circuits
App 20150347659 - CHIANG; Ting-Wei ; et al. | 2015-12-03 |
Adding Decoupling Function for TAP Cells
App 20150318407 - Chen; Kuo-Ji ; et al. | 2015-11-05 |
Distributed Metal Routing
App 20150255338 - Xiao; You-Cheng ; et al. | 2015-09-10 |
Method And Apparatus For Forming An Integrated Circuit With A Metalized Resistor In A Standard Cell Configuration
App 20150249080 - MA; Wei Yu ; et al. | 2015-09-03 |
Masks formed based on integrated circuit layout design having standard cell that includes extended active region
Grant 9,123,565 - Lu , et al. September 1, 2 | 2015-09-01 |
Non-hierarchical metal layers for integrated circuits
Grant 9,117,882 - Lu , et al. August 25, 2 | 2015-08-25 |
Integrated circuit
Grant 9,105,466 - Lu , et al. August 11, 2 | 2015-08-11 |
Layout of an integrated circuit
Grant 9,098,668 - Tien , et al. August 4, 2 | 2015-08-04 |
Cell layout design and method
Grant 9,087,170 - Hsu , et al. July 21, 2 | 2015-07-21 |
Adding decoupling function for tap cells
Grant 9,082,886 - Chen , et al. July 14, 2 | 2015-07-14 |
Method of forming edge devices for improved performance
Grant 9,064,799 - Chen , et al. June 23, 2 | 2015-06-23 |
Method and Layout of an Integrated Circuit
App 20150171005 - Chen; Wei-Yu ; et al. | 2015-06-18 |
Connecting Techniques For Stacked Cmos Devices
App 20150162295 - Tseng; Hsiang-Jen ; et al. | 2015-06-11 |
Layout Of An Integrated Circuit
App 20150149976 - Tien; Li-Chun ; et al. | 2015-05-28 |
Distributed metal routing
Grant 9,041,069 - Xiao , et al. May 26, 2 | 2015-05-26 |
Method and apparatus for forming an integrated circuit with a metalized resistor in a standard cell configuration
Grant 9,035,393 - Ma , et al. May 19, 2 | 2015-05-19 |
Multi-patterning conflict free integrated circuit design
Grant 9,026,971 - Ho , et al. May 5, 2 | 2015-05-05 |
System and method for arbitrary metal spacing for self-aligned double patterning
Grant 9,026,973 - Tien , et al. May 5, 2 | 2015-05-05 |
Methods for Double-Patterning-Compliant Standard Cell Design
App 20150095870 - Chen; Huang-Yu ; et al. | 2015-04-02 |
Cell Layout Design And Method
App 20150067616 - HSU; Chin-Hsiung ; et al. | 2015-03-05 |
Standard Cell Layout, Semiconductor Device Having Engineering Change Order (eco) Cells And Method
App 20150048424 - TIEN; Li-Chun ; et al. | 2015-02-19 |
Method And Layout Of An Integrated Circuit
App 20150035070 - Chiang; Ting-Wei ; et al. | 2015-02-05 |
Memory Cell Array
App 20150021701 - CHANG; Shi-Wei ; et al. | 2015-01-22 |
Methods for double-patterning-compliant standard cell design
Grant 8,907,441 - Chen , et al. December 9, 2 | 2014-12-09 |
Method And Layout Of An Integrated Circuit
App 20140332971 - TSENG; Hsiang-Jen ; et al. | 2014-11-13 |
Standard Cell Design Layout
App 20140298284 - Hsu; Chin-Hsiung ; et al. | 2014-10-02 |
System And Method For Arbitrary Metal Spacing For Self-aligned Double Patterning
App 20140264894 - TIEN; Li-Chun ; et al. | 2014-09-18 |
Cell Boundaries For Self Aligned Multiple Patterning Abutments
App 20140282289 - Hsu; Chin-Hsiung ; et al. | 2014-09-18 |
Method and apparatus for word line decoder layout
Grant 8,837,250 - Xiao , et al. September 16, 2 | 2014-09-16 |
Efficient semiconductor device cell layout utilizing underlying local connective features
Grant 8,816,403 - Chen , et al. August 26, 2 | 2014-08-26 |
Method and layout of an integrated circuit
Grant 8,819,610 - Tseng , et al. August 26, 2 | 2014-08-26 |
Multiple via connections using connectivity rings
Grant 8,813,016 - Hsu , et al. August 19, 2 | 2014-08-19 |
Self-aligned multiple patterning layout design
Grant 8,799,834 - Chen , et al. August 5, 2 | 2014-08-05 |
Method And Apparatus For Forming An Integrated Circuit With A Metalized Resistor In A Standard Cell Configuration
App 20140210014 - MA; Wei Yu ; et al. | 2014-07-31 |
Self-aligned Multiple Patterning Layout Design
App 20140215421 - Chen; Huang-Yu ; et al. | 2014-07-31 |
Adaptive Fin Design for FinFETs
App 20140203378 - Ou; Tsong-Hua ; et al. | 2014-07-24 |
Method And Layout Of An Integrated Circuit
App 20140195997 - TSENG; Hsiang-Jen ; et al. | 2014-07-10 |
Integrated Circuit Layout Design
App 20140183647 - LU; Lee-Chung ; et al. | 2014-07-03 |
Adaptive fin design for FinFETs
Grant 8,728,892 - Ou , et al. May 20, 2 | 2014-05-20 |
Integrated Circuit Layout
App 20140109033 - CHERN; Chan-Hong ; et al. | 2014-04-17 |
Integrated Circuit
App 20140077270 - LU; Lee-Chung ; et al. | 2014-03-20 |
Edge Devices Layout For Improved Performance
App 20140073124 - CHEN; Yen-Huei ; et al. | 2014-03-13 |
Memory edge cell
Grant 8,665,654 - Cheng , et al. March 4, 2 | 2014-03-04 |
Systems and methods of designing integrated circuits
Grant 8,661,389 - Chern , et al. February 25, 2 | 2014-02-25 |
Integrated circuit design using DFM-enhanced architecture
Grant 8,631,366 - Hou , et al. January 14, 2 | 2014-01-14 |
Layout Architecture for Performance Improvement
App 20140001595 - Lu; Lee-Chung ; et al. | 2014-01-02 |
Edge devices layout for improved performance
Grant 8,610,236 - Chen , et al. December 17, 2 | 2013-12-17 |
Integrated circuits and methods of designing the same
Grant 8,607,172 - Lu , et al. December 10, 2 | 2013-12-10 |
Memory Edge Cell
App 20130286708 - CHENG; Hong-Chen ; et al. | 2013-10-31 |
Integrated circuit layouts with power rails under bottom metal layer
Grant 8,507,957 - Hou , et al. August 13, 2 | 2013-08-13 |
Standard cells having flexible layout architecture/boundaries
Grant 8,504,972 - Hou , et al. August 6, 2 | 2013-08-06 |
Memory edge cell
Grant 8,482,990 - Cheng , et al. July 9, 2 | 2013-07-09 |
Systems and methods of designing integrated circuits
Grant 8,473,888 - Guo , et al. June 25, 2 | 2013-06-25 |
Layouts of POLY cut openings overlapping active regions
Grant 8,455,354 - Chen , et al. June 4, 2 | 2013-06-04 |
Layout and process of forming contact plugs
Grant 8,431,985 - Hou , et al. April 30, 2 | 2013-04-30 |
Integrated Circuits And Methods Of Designing The Same
App 20130087932 - LU; Lee-Chung ; et al. | 2013-04-11 |
Method and apparatus for achieving multiple patterning technology compliant design layout
Grant 8,418,111 - Chen , et al. April 9, 2 | 2013-04-09 |
Method For Checking And Fixing Double-patterning Layout
App 20130080980 - WANG; Dio ; et al. | 2013-03-28 |
Efficient Semiconductor Device Cell Layout Utilizing Underlying Local Connective Features
App 20130069236 - Chen; Jung-Hsuan ; et al. | 2013-03-21 |
Method for checking and fixing double-patterning layout
Grant 8,365,102 - Wang , et al. January 29, 2 | 2013-01-29 |
Cell architecture and method
Grant 8,356,262 - Lu , et al. January 15, 2 | 2013-01-15 |
Cell Architecture And Method
App 20120331426 - LU; Lee-Chung ; et al. | 2012-12-27 |
Non-Hierarchical Metal Layers for Integrated Circuits
App 20120313256 - Lu; Lee-Chung ; et al. | 2012-12-13 |
Adding Decoupling Function for TAP Cells
App 20120286341 - Chen; Kuo-Ji ; et al. | 2012-11-15 |
Integrated Circuit Layouts with Power Rails under Bottom Metal Layer
App 20120280287 - Hou; Yung-Chin ; et al. | 2012-11-08 |
Adaptive Fin Design for FinFETs
App 20120280331 - Ou; Tsong-Hua ; et al. | 2012-11-08 |
Systems And Methods Of Designing Integrated Circuits
App 20120266126 - CHERN; Chan-Hong ; et al. | 2012-10-18 |
Layouts of POLY Cut Openings Overlapping Active Regions
App 20120258592 - Chen; Jung-Hsuan ; et al. | 2012-10-11 |
Systems And Methods Of Designing Integrated Circuits
App 20120240088 - GUO; Ta-Pen ; et al. | 2012-09-20 |
Methods for cell boundary isolation in double patterning design
Grant 8,255,837 - Lu , et al. August 28, 2 | 2012-08-28 |
Memory Edge Cell
App 20120206953 - CHENG; Hong-Chen ; et al. | 2012-08-16 |
Distributed Metal Routing
App 20120181707 - Xiao; You-Cheng ; et al. | 2012-07-19 |
Contact implement structure for high density design
Grant 8,217,469 - Hou , et al. July 10, 2 | 2012-07-10 |
Method And Apparatus For Achieving Multiple Patterning Technology Compliant Design Layout
App 20120131528 - Chen; Huang-Yu ; et al. | 2012-05-24 |
Layout and Process of Forming Contact Plugs
App 20120032268 - Hou; Yung-Chin ; et al. | 2012-02-09 |
Edge Devices Layout For Improved Performance
App 20120032293 - CHEN; Yen-Huei ; et al. | 2012-02-09 |
Method And Apparatus For Word Line Decoder Layout
App 20120020179 - XIAO; You-Cheng ; et al. | 2012-01-26 |
Method For Checking And Fixing Double-patterning Layout
App 20110296360 - WANG; Dio ; et al. | 2011-12-01 |
Integrated Circuits And Manufacturing Methods Thereof
App 20110291200 - KESHAVARZI; Ali ; et al. | 2011-12-01 |
Methods for Double-Patterning-Compliant Standard Cell Design
App 20110193234 - Chen; Huang-Yu ; et al. | 2011-08-11 |
Place-and-route layout method with same footprint cells
Grant 7,966,596 - Lu , et al. June 21, 2 | 2011-06-21 |
Novel Contact Implement Structure For High Density Design
App 20110140203 - Hou; Yung-Chin ; et al. | 2011-06-16 |
Structure and system of mixing poly pitch cell design under default poly pitch design rules
Grant 7,932,566 - Hou , et al. April 26, 2 | 2011-04-26 |
Integrated Circuit Design using DFM-Enhanced Architecture
App 20100281446 - Hou; Yung-Chin ; et al. | 2010-11-04 |
Layout architecture for improving circuit performance
Grant 7,821,039 - Tien , et al. October 26, 2 | 2010-10-26 |
Standard Cells Having Flexible Layout Architecture/Boundaries
App 20100269081 - Hou; Yung-Chin ; et al. | 2010-10-21 |
Standard cell without OD space effect in Y-direction
Grant 7,808,051 - Hou , et al. October 5, 2 | 2010-10-05 |
Methods for Cell Boundary Isolation in Double Patterning Design
App 20100196803 - Lu; Lee-Chung ; et al. | 2010-08-05 |
Structure and System of Mixing Poly Pitch Cell Design under Default Poly Pitch Design Rules
App 20100164614 - Hou; Yung-Chin ; et al. | 2010-07-01 |
Novel Layout Architecture For Performance Enhancement
App 20100127333 - Hou; Yung-Chin ; et al. | 2010-05-27 |
Standard Cell without OD Space Effect in Y-Direction
App 20100078725 - Hou; Yung-Chin ; et al. | 2010-04-01 |
Place-and-route Layout Method With Same Footprint Cells
App 20100058267 - Lu; Lee-Chung ; et al. | 2010-03-04 |
Layout Architecture for Improving Circuit Performance
App 20090315079 - Tien; Li-Chun ; et al. | 2009-12-24 |
Method for automatically modifying integrated circuit layout
Grant 7,496,862 - Chang , et al. February 24, 2 | 2009-02-24 |
ECO cell for reducing leakage power
Grant 7,458,051 - Hou , et al. November 25, 2 | 2008-11-25 |
Voltage level shifter with single well voltage
App 20080143418 - Lu; Lee-Chung ; et al. | 2008-06-19 |
Method for automatically modifying integrated circuit layout
App 20080059916 - Chang; Mi-Chang ; et al. | 2008-03-06 |
Transistor layout for standard cell with optimized mechanical stress effect
Grant 7,321,139 - Chang , et al. January 22, 2 | 2008-01-22 |
Transistor layout for standard cell with optimized mechanical stress effect
App 20070284618 - Chang; Mi-Chang ; et al. | 2007-12-13 |
Very fine-grain voltage island integrated circuit
Grant 7,247,894 - Hou , et al. July 24, 2 | 2007-07-24 |
ECO cell for reducing leakage power
App 20070109832 - Hou; Yung-Chin ; et al. | 2007-05-17 |
Method for reducing layers revision in engineering change order
Grant 7,137,094 - Tien November 14, 2 | 2006-11-14 |
Method of defining forbidden pitches for a lithography exposure tool
Grant 6,973,636 - Shin , et al. December 6, 2 | 2005-12-06 |
Variable layout design for multiple voltage applications
Grant 6,903,389 - Tai , et al. June 7, 2 | 2005-06-07 |
Efficient source diffusion interconnect, MOS transistor and standard cell layout utilizing same
Grant 6,849,904 - Tien , et al. February 1, 2 | 2005-02-01 |
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