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name:-0.10754108428955
name:-0.042999982833862
name:-0.011831998825073
TIEN; Bor-Zen Patent Filings

TIEN; Bor-Zen

Patent Applications and Registrations

Patent applications and USPTO patent grants for TIEN; Bor-Zen.The latest application filed is for "semiconductor device and manufacturing method thereof".

Company Profile
11.37.37
  • TIEN; Bor-Zen - Hsinchu City TW
  • Tien; Bor-Zen - Hsinchu TW
  • Tien; Bor-Zen - Hsin-Chu TW
  • Tien; Bor-Zen - Shang-Shung TW
  • Tien; Bor-Zen - Shang-Shung Village TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor Device And Manufacturing Method Thereof
App 20210359085 - PENG; Cheng-Yi ;   et al.
2021-11-18
Method Of Manufacturing Semiconductor Devices And Semiconductor Devices
App 20210351282 - PENG; Cheng-Yi ;   et al.
2021-11-11
Method of manufacturing a semiconductor device and a semiconductor device
Grant 11,101,360 - Peng , et al. August 24, 2
2021-08-24
Semiconductor device and manufacturing method thereof
Grant 11,075,269 - Peng , et al. July 27, 2
2021-07-27
Method of manufacturing semiconductor devices and semiconductor devices
Grant 11,069,791 - Peng , et al. July 20, 2
2021-07-20
Method for forming interconnect structure
Grant 11,011,419 - Tien , et al. May 18, 2
2021-05-18
Methods for manufacturing semiconductor arrangements using photoresist masks
Grant 10,957,653 - Chiang , et al. March 23, 2
2021-03-23
Systems and methods to enhance passivation integrity
Grant 10,777,480 - Liao , et al. Sept
2020-09-15
Method for Forming Interconnect Structure
App 20200227316 - Tien; Bor-Zen ;   et al.
2020-07-16
Semiconductor Device And Manufacturing Method Thereof
App 20200176566 - PENG; Cheng-Yi ;   et al.
2020-06-04
Method Of Manufacturing A Semiconductor Device And A Semiconductor Device
App 20200168716 - PENG; Cheng-Yi ;   et al.
2020-05-28
Method Of Manufacturing Semiconductor Devices And Semiconductor Devices
App 20200135891 - PENG; Cheng-Yi ;   et al.
2020-04-30
Method for forming interconnect structure
Grant 10,629,481 - Tien , et al.
2020-04-21
Systems And Methods To Enhance Passivation Integrity
App 20200111719 - Liao; Ying-Chieh ;   et al.
2020-04-09
Multi-height Semiconductor Structures
App 20200043859 - CHIANG; Tsung-Yu ;   et al.
2020-02-06
Systems and methods to enhance passivation integrity
Grant 10,515,866 - Liao , et al. Dec
2019-12-24
Back-end-of-line (BEOL) arrangement with multi-height interlayer dielectric (ILD) structures
Grant 10,515,902 - Chiang , et al. Dec
2019-12-24
Semiconductor device and method of fabricating the same
Grant 10,347,766 - Ho , et al. July 9, 2
2019-07-09
Systems And Methods To Enhance Passivation Integrity
App 20190115273 - Liao; Ying-Chieh ;   et al.
2019-04-18
Systems and methods to enhance passivation integrity
Grant 10,157,810 - Liao , et al. Dec
2018-12-18
Mechanisms for forming FinFETs with different fin heights
Grant 10,134,626 - Chiang , et al. November 20, 2
2018-11-20
Semiconductor device with self-protecting fuse and method of fabricating the same
Grant 10,014,251 - Lai , et al. July 3, 2
2018-07-03
Multi-height Semiconductor Structures
App 20180138129 - CHIANG; Tsung-Yu ;   et al.
2018-05-17
Mechanisms For Forming Finfets With Different Fin Heights
App 20180102278 - CHIANG; Tsung-Yu ;   et al.
2018-04-12
Semiconductor arrangement having an overlay alignment mark with a height shorter than a neighboring gate structure
Grant 9,870,998 - Chiang , et al. January 16, 2
2018-01-16
Systems And Methods To Enhance Passivation Integrity
App 20180012818 - Liao; Ying-Chieh ;   et al.
2018-01-11
Mechanisms for forming FinFETs with different fin heights
Grant 9,842,761 - Chiang , et al. December 12, 2
2017-12-12
Method for Forming Interconnect Structure
App 20170323827 - Tien; Bor-Zen ;   et al.
2017-11-09
Systems and methods to enhance passivation integrity
Grant 9,773,716 - Liao , et al. September 26, 2
2017-09-26
Method for forming interconnect structure
Grant 9,716,034 - Tien , et al. July 25, 2
2017-07-25
Mechanisms For Forming Finfets With Different Fin Heights
App 20170140980 - CHIANG; Tsung-Yu ;   et al.
2017-05-18
Mechanisms for forming FinFETs with different fin heights
Grant 9,559,011 - Chiang , et al. January 31, 2
2017-01-31
Methods and apparatus of metal gate transistors
Grant 9,508,590 - Chiang , et al. November 29, 2
2016-11-29
Systems And Methods To Enhance Passivation Integrity
App 20160247741 - Liao; Ying-Chieh ;   et al.
2016-08-25
BEOL selectivity stress film
Grant 9,412,866 - Kuoh , et al. August 9, 2
2016-08-09
Semiconductor Device With Self-protecting Fuse And Method Of Fabricating The Same
App 20160190064 - LAI; Chen-Chung ;   et al.
2016-06-30
Systems and methods to enhance passivation integrity
Grant 9,349,688 - Liao , et al. May 24, 2
2016-05-24
Methods and Apparatus of Metal Gate Transistors
App 20160133509 - Chiang; Tsung-Yu ;   et al.
2016-05-12
Semiconductor device with self-protecting fuse and method of fabricating the same
Grant 9,299,658 - Lai , et al. March 29, 2
2016-03-29
Smart measurement techniques to enhance inline process control stability
Grant 9,299,621 - Yang , et al. March 29, 2
2016-03-29
Semiconductor Device And Method Of Fabricating The Same
App 20160064567 - HO; Wei-Shuo ;   et al.
2016-03-03
Mechanisms For Forming Finfets With Different Fin Heights
App 20160043003 - CHIANG; Tsung-Yu ;   et al.
2016-02-11
Multi-height Semiconductor Structures
App 20160043038 - Chiang; Tsung-Yu ;   et al.
2016-02-11
Method for Forming Interconnect Structure
App 20160042992 - Tien; Bor-Zen ;   et al.
2016-02-11
Methods and apparatus of metal gate transistors
Grant 9,252,259 - Chiang , et al. February 2, 2
2016-02-02
Method for forming interconnect structure
Grant 9,190,319 - Lin , et al. November 17, 2
2015-11-17
Mechanisms for forming FinFETs with different fin heights
Grant 9,184,087 - Chiang , et al. November 10, 2
2015-11-10
Methods for forming a semiconductor arrangement with structures having different heights
Grant 9,178,066 - Chiang , et al. November 3, 2
2015-11-03
Systems And Methods To Enhance Passivation Integrity
App 20150311156 - Liao; Ying-Chieh ;   et al.
2015-10-29
Semiconductor Device With Self-protecting Fuse And Method Of Fabricating The Same
App 20150255394 - LAI; Chen-Chung ;   et al.
2015-09-10
Apparatus and method for designing an integrated circuit layout having a plurality of cell technologies
Grant 9,122,828 - Chiang , et al. September 1, 2
2015-09-01
Conductive diffusion barrier structure for ohmic contacts
Grant 9,093,373 - Chang , et al. July 28, 2
2015-07-28
Stress compensation layer to improve device uniformity
Grant 9,093,528 - Peng , et al. July 28, 2
2015-07-28
Systems and methods to enhance passivation integrity
Grant 9,076,804 - Liao , et al. July 7, 2
2015-07-07
Mechanisms For Forming Finfets With Different Fin Heights
App 20150187634 - CHIANG; Tsung-Yu ;   et al.
2015-07-02
Semiconductor device with self-protecting fuse
Grant 9,070,687 - Lai , et al. June 30, 2
2015-06-30
Smart Measurement Techniques to Enhance Inline Process Control Stability
App 20150069395 - Yang; Han-Wei ;   et al.
2015-03-12
Multi-height Semiconductor Structures
App 20150061016 - Chiang; Tsung-Yu ;   et al.
2015-03-05
Systems and Methods to Enhance Passivation Integrity
App 20150054163 - Liao; Ying-Chieh ;   et al.
2015-02-26
Conductive Diffusion Barrier Structure For Ohmic Contacts
App 20150048507 - Chang; Chin-Chia ;   et al.
2015-02-19
Semiconductor Device With Self-Protecting Fuse And Method Of Fabricating The Same
App 20150001592 - Lai; Chen-Chung ;   et al.
2015-01-01
Beol Selectivity Stress Film
App 20140374832 - Kuoh; Gwo-Chyuan ;   et al.
2014-12-25
Stress Compensation Layer to Improve Device Uniformity
App 20140353833 - Peng; Yen-Ming ;   et al.
2014-12-04
Apparatus And Method For Designing An Integrated Circuit Layout Having A Plurality Of Cell Technologies
App 20140344770 - CHIANG; Tsung-Yu ;   et al.
2014-11-20
Semiconductor device having a spacer and a liner overlying a sidewall of a gate structure and method of forming the same
Grant 8,860,151 - Chen , et al. October 14, 2
2014-10-14
Method For Forming Interconnect Structure
App 20140252621 - Lin; Hsuan-Han ;   et al.
2014-09-11
Semiconductor Device Having A Spacer And A Liner Overlying A Sidewall Of A Gate Structure And Method Of Forming The Same
App 20140246709 - Chen; Sheng-Ching ;   et al.
2014-09-04
Methods and Apparatus of Metal Gate Transistors
App 20140231932 - Chiang; Tsung-Yu ;   et al.
2014-08-21
Method to reduce leakage in a protection diode structure
Grant 7,998,772 - Tien , et al. August 16, 2
2011-08-16
Method to reduce leakage in a protection diode structure
App 20100081249 - Tien; Bor-Zen ;   et al.
2010-04-01
Semiconductor device with reduced leakage protection diode
Grant 7,663,164 - Tien , et al. February 16, 2
2010-02-16
Method to reduce leakage in a protection diode structure
App 20060163657 - Tien; Bor-Zen ;   et al.
2006-07-27
Non-distort spacer profile during subsequent processing
Grant 6,346,449 - Chang , et al. February 12, 2
2002-02-12
Method to improve TiSix salicide formation
Grant 6,294,448 - Chang , et al. September 25, 2
2001-09-25

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