Thusoo; Shalesh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Thusoo; Shalesh.The latest application filed is for "area efficient bist system for memories".

Company Profile

0.18.2

Thusoo; Shalesh - San Jose CA
Thusoo; Shalesh - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor Grant 8,065,504 - Yates, Jr. , et al. November 22, 2	2011-11-22
Area efficient BIST system for memories Grant 7,240,255 - Njinda , et al. July 3, 2	2007-07-03
Managing instruction side-effects Grant 7,228,404 - Patel , et al. June 5, 2	2007-06-05
Area efficient BIST system for memories App 20060218452 - Njinda; Charles Akum ; et al.	2006-09-28
Profiling execution of computer programs Grant 7,013,456 - Van Dyke , et al. March 14, 2	2006-03-14
Profiling of computer programs executing in virtual memory systems Grant 6,941,545 - Reese , et al. September 6, 2	2005-09-06
Exception mechanism for a computer Grant 6,934,832 - Van Dyke , et al. August 23, 2	2005-08-23
Table look-up for control of instruction execution App 20050086451 - Yates, John S. JR. ; et al.	2005-04-21
Profiling program execution into registers of a computer Grant 6,826,748 - Hohensee , et al. November 30, 2	2004-11-30
Method and apparatus for out of order memory processing within an in order processor Grant 6,775,756 - Thusoo , et al. August 10, 2	2004-08-10
Method of manufacture and apparatus of an integrated computing system Grant 6,643,726 - Patkar , et al. November 4, 2	2003-11-04
Multi-branch resolution Grant 6,578,134 - Van Dyke , et al. June 10, 2	2003-06-10
Method and apparatus for busing data elements Grant 6,449,671 - Patkar , et al. September 10, 2	2002-09-10
Method and apparatus for interfacing a processor with a bus Grant 6,430,646 - Thusoo , et al. August 6, 2	2002-08-06
Method and apparatus for providing probe based bus locking and address locking Grant 6,389,519 - Thusoo , et al. May 14, 2	2002-05-14
Debug and video queue for multi-processor chip Grant 5,848,264 - Baird , et al. December 8, 1	1998-12-08
Pipelined processor for executing repeated string instructions by halting dispatch after comparision to pipeline capacity Grant 5,822,602 - Thusoo October 13, 1	1998-10-13
Early instruction-length pre-decode of variable-length instructions in a superscalar processor Grant 5,809,272 - Thusoo , et al. September 15, 1	1998-09-15
Mixed-modulo address generation using shadow segment registers Grant 5,790,443 - Shen , et al. August 4, 1	1998-08-04
Stack push/pop tracking and pairing in a pipelined processor Grant 5,687,336 - Shen , et al. November 11, 1	1997-11-11

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