loadpatents
name:-0.00565505027771
name:-0.01826000213623
name:-0.0005340576171875
Thoma; Nandor G. Patent Filings

Thoma; Nandor G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Thoma; Nandor G..The latest application filed is for "single-event upset tolerant static random access memory cell".

Company Profile
0.14.3
  • Thoma; Nandor G. - Vero Beach FL
  • Thoma; Nandor G. - Manassas VA
  • Thoma; Nandor G. - Plano TX
  • Thoma; Nandor G. - Austin TX
  • Thoma; Nandor G. - Boca Raton FL
  • Thoma; Nandor G. - Jericho VT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Single-event upset tolerant static random access memory cell
App 20060133134 - Doyle; Scott E. ;   et al.
2006-06-22
Ring oscillator providing single event transient immunity
Grant 6,642,802 - Knowles , et al. November 4, 2
2003-11-04
Ring oscillator providing single event transient immunity
App 20030117221 - Knowles, Kenneth R. ;   et al.
2003-06-26
Single-event upset tolerant latch for sense amplifiers
App 20020018372 - Thoma, Nandor G. ;   et al.
2002-02-14
High speed pipeline method and apparatus
Grant 5,732,233 - Klim , et al. March 24, 1
1998-03-24
Hierarchical clocking system using adaptive feedback
Grant 5,619,158 - Casal , et al. April 8, 1
1997-04-08
Symmetric clock system for a data processing system including dynamically switchable frequency divider
Grant 5,524,035 - Casal , et al. June 4, 1
1996-06-04
Electronically tuneable computer clocking system and method of electronically tuning distribution lines of a computer clocking system
Grant 5,442,776 - Masleid , et al. August 15, 1
1995-08-15
Microword generation mechanism utilizing a separate branch decision programmable logic array
Grant 4,947,369 - Thoma , et al. August 7, 1
1990-08-07
Differential cascode voltage switch (DCVS) master slice for high efficiency/custom density physical design
Grant 4,608,649 - Davis , et al. * August 26, 1
1986-08-26
Clocking mechanism for multiple overlapped dynamic programmable logic arrays used in a digital control unit
Grant 4,575,794 - Veneski , et al. March 11, 1
1986-03-11
Large scale integration data processor signal transfer mechanism
Grant 4,567,561 - Wyatt , et al. January 28, 1
1986-01-28
Tristate driver circuit with low standby power consumption
Grant 4,488,067 - Kraft , et al. December 11, 1
1984-12-11
Apparatus and method for decoding an operation code using a plurality of multiplexed programmable logic arrays
Grant 4,484,268 - Thoma , et al. November 20, 1
1984-11-20
Logic performing cell for use in array structures
Grant 4,395,646 - Cases , et al. July 26, 1
1983-07-26
V-MOS Device with self-aligned multiple electrodes
Grant 4,364,074 - Garnache , et al. December 14, 1
1982-12-14
Object Handling Fixture, System, And Process
Grant 3,811,182 - Ryan, Sr. , et al. May 21, 1
1974-05-21

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