Thees; Hans-Jurgen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Thees; Hans-Jurgen.The latest application filed is for "differential sg/eg spacer integration with equivalent nfet/pfet spacer widths & dual raised source drain expitaxial silicon and ".

Company Profile

0.7.11

Thees; Hans-Jurgen - Dresden DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI Grant 11,217,678 - Mulfinger , et al. January 4, 2	2022-01-04
Differential Sg/eg Spacer Integration With Equivalent Nfet/pfet Spacer Widths & Dual Raised Source Drain Expitaxial Silicon And App 20200083346 - MULFINGER; George Robert ; et al.	2020-03-12
Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dial raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI Grant 10,522,655 - Mulfinger , et al. Dec	2019-12-31
Semiconductor device structure with self-aligned capacitor device Grant 10,418,364 - Baars , et al. Sept	2019-09-17
Semiconductor Device Structure With Self-aligned Capacitor Device App 20180061839 - Baars; Peter ; et al.	2018-03-01
Differential Sg/eg Spacer Integration With Equivalent Nfet/pfet Spacer Widths & Dual Raised Source Drain Expitaxial Silicon And Triple-nitride Spacer Integration Enabling High-voltage Eg Device On Fdsoi App 20180012973 - MULFINGER; George Robert ; et al.	2018-01-11
Differential Sg/eg Spacer Integration With Equivalent Nfet/pfet Spacer Widths & Dual Raised Source Drain Expitaxial Silicon And Triple-nitride Spacer Integration Enabling High-voltage Eg Device On Fdsoi App 20170330953 - MULFINGER; George Robert ; et al.	2017-11-16
Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI Grant 9,806,170 - Mulfinger , et al. October 31, 2	2017-10-31
Epitaxial growth of silicon for FinFETS with non-rectangular cross-sections Grant 9,324,868 - Yan , et al. April 26, 2	2016-04-26
Epitaxial Growth Of Silicon For Finfets With Non-rectangular Cross-sections App 20160056294 - YAN; Ran Ruby ; et al.	2016-02-25
Processes for forming integrated circuits and integrated circuits formed thereby Grant 8,906,801 - Richter , et al. December 9, 2	2014-12-09
Processes For Forming Integrated Circuits And Integrated Circuits Formed Thereby App 20130234336 - Richter; Ralf ; et al.	2013-09-12
Methods For Fabricating Semiconductor Devices With Reduced Damage To Shallow Trench Isolation (sti) Regions App 20130189821 - Thees; Hans-Jurgen ; et al.	2013-07-25
Method Of Forming A Semiconductor Device App 20130037866 - Thees; Hans-Jurgen ; et al.	2013-02-14

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.