Thean; Voon Yew

Patent Applications and Registrations

Patent applications and USPTO patent grants for Thean; Voon Yew.The latest application filed is for "methods and mask structures for substantially defect-free epitaxial growth".

Company Profile

1.60.64

Thean; Voon Yew - Brussels BE
Thean; Voon Yew - Tervuren BE
Thean; Voon Yew - Brussel BE
Thean; Voon-Yew - Hopewell Junction NY US
Thean; Voon-Yew - Fishkill NY
Thean; Voon-Yew - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and mask structures for substantially defect-free epitaxial growth Grant 10,340,139 - Vincent , et al.	2019-07-02
FET biosensor Grant 10,309,925 - Collaert , et al.	2019-06-04
Ferroelectric memory device and fabrication method thereof Grant 10,211,312 - Van Houdt , et al. Feb	2019-02-19
Methods and Mask Structures for Substantially Defect-Free Epitaxial Growth App 20170040168 - Vincent; Benjamin ; et al.	2017-02-09
Ferroelectric Memory Device And Fabrication Method Thereof App 20170040331 - Van Houdt; Jan ; et al.	2017-02-09
Fet Biosensor App 20160320336 - COLLAERT; Nadine ; et al.	2016-11-03
Methods using mask structures for substantially defect-free epitaxial growth Grant 9,476,143 - Vincent , et al. October 25, 2	2016-10-25
FinFET device with dual-strained channels and method for manufacturing thereof Grant 9,368,498 - Eneman , et al. June 14, 2	2016-06-14
FinFET DEVICE WITH DUAL-STRAINED CHANNELS AND METHOD FOR MANUFACTURING THEREOF App 20160027777 - ENEMAN; Geert ; et al.	2016-01-28
FinFET device with dual-strained channels and method for manufacturing thereof Grant 9,171,904 - Eneman , et al. October 27, 2	2015-10-27
FinFET DEVICE WITH DUAL-STRAINED CHANNELS AND METHOD FOR MANUFACTURING THEREOF App 20140151766 - Eneman; Geert ; et al.	2014-06-05
Spacer protection and electrical connection for array device Grant 8,623,714 - Park , et al. January 7, 2	2014-01-07
Method of forming a semiconductor device featuring a gate stressor and semiconductor device Grant 8,587,039 - Winstead , et al. November 19, 2	2013-11-19
Integrated circuit structure having substantially planar N-P step height and methods of forming Grant 8,563,394 - Li , et al. October 22, 2	2013-10-22
Integrated Circuit Structure Having Substantially Planar N-p Step Height And Methods Of Forming App 20120256268 - Li; Weipeng ; et al.	2012-10-11
Balancing NFET and PFET performance using straining layers Grant 8,106,462 - Chen , et al. January 31, 2	2012-01-31
Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit Grant 8,039,341 - Thean , et al. October 18, 2	2011-10-18
Spacer Protection And Electrical Connection For Array Device App 20110227136 - Park; Jae-Eun ; et al.	2011-09-22
Method Of Forming A Semiconductor Device Featuring A Gate Stressor And Semiconductor Device App 20110220975 - Winstead; Brian A. ; et al.	2011-09-15
CMOS process with optimized PMOS and NMOS transistor devices Grant 8,003,454 - Zhang , et al. August 23, 2	2011-08-23
Balancing Nfet And Pfet Performance Using Straining Layers App 20110169096 - Chen; Xiangdong ; et al.	2011-07-14
Method of forming a semiconductor device featuring a gate stressor and semiconductor device Grant 7,960,243 - Winstead , et al. June 14, 2	2011-06-14
Semiconductor device with selectively modulated gate work function Grant 7,911,002 - Thean , et al. March 22, 2	2011-03-22
Method for transistor fabrication with optimized performance Grant 7,883,953 - Zhang , et al. February 8, 2	2011-02-08
Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors Grant 7,867,839 - Chen , et al. January 11, 2	2011-01-11
Electronic devices including a semiconductor layer Grant 7,821,067 - Thean , et al. October 26, 2	2010-10-26
Method for forming a semiconductor structure having a strained silicon layer Grant 7,811,382 - Sadaka , et al. October 12, 2	2010-10-12
Twisted dual-substrate orientation (DSO) substrates Grant 7,803,670 - White , et al. September 28, 2	2010-09-28
Semiconductor Device With Selectively Modulated Gate Work Function App 20100230756 - Thean; Voon-Yew ; et al.	2010-09-16
Structure and method for strained transistor directly on insulator Grant 7,781,839 - Thean , et al. August 24, 2	2010-08-24
Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit Grant 7,781,277 - Nguyen , et al. August 24, 2	2010-08-24
Semiconductor device structure Grant 7,781,840 - White , et al. August 24, 2	2010-08-24
Method for PFET enhancement Grant 7,763,510 - Zhang , et al. July 27, 2	2010-07-27
Method For Pfet Enhancement App 20100171180 - Zhang; Da ; et al.	2010-07-08
Method of making a semiconductor device with embedded stressor Grant 7,736,957 - Grudowski , et al. June 15, 2	2010-06-15
Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer Grant 7,737,018 - Mathew , et al. June 15, 2	2010-06-15
Metal Gate Transistors App 20100102393 - LEE; James Yong Meng ; et al.	2010-04-29
Integrated circuit with different channel materials for P and N channel transistors and method therefor Grant 7,700,420 - Thean , et al. April 20, 2	2010-04-20
Method for Transistor Fabrication with Optimized Performance App 20100078687 - Zhang; Da ; et al.	2010-04-01
Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer Grant 7,659,156 - Thean , et al. February 9, 2	2010-02-09
Planar Double Gate Transistor Storage Cell App 20100027355 - Dao; Thuy B. ; et al.	2010-02-04
METHOD TO REDUCE THRESHOLD VOLTAGE (Vt) IN SILICON GERMANIUM (SIGE), HIGH-K DIELECTRIC-METAL GATE, P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS App 20100013021 - Chen; Xiangdong ; et al.	2010-01-21
Method for Making Transistors and the Device Thereof App 20090289280 - Zhang; Da ; et al.	2009-11-26
CMOS Process with Optimized PMOS and NMOS Transistor Devices App 20090291540 - Zhang; Da ; et al.	2009-11-26
Modulation of Tantalum-Based Electrode Workfunction App 20090286387 - Gilmer; David C. ; et al.	2009-11-19
Method for forming a semiconductor structure and structure thereof Grant 7,615,806 - Thean , et al. November 10, 2	2009-11-10
Asymmetric spacers and asymmetric source/drain extension layers Grant 7,585,735 - Mathew , et al. September 8, 2	2009-09-08
Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer Grant 7,575,975 - Thean , et al. August 18, 2	2009-08-18
Method for forming vertical structures in a semiconductor device Grant 7,556,992 - Shi , et al. July 7, 2	2009-07-07
Semiconductor optical devices having fin structures Grant 7,521,720 - Mathew , et al. April 21, 2	2009-04-21
Semiconductor optical devices and method for forming Grant 7,494,832 - Mathew , et al. February 24, 2	2009-02-24
Engineering strain in thick strained-SOI substrates Grant 7,468,313 - Thean , et al. December 23, 2	2008-12-23
Method Of Forming A Semiconductor Device Featuring A Gate Stressor And Semiconductor Device App 20080299717 - Winstead; Brian A. ; et al.	2008-12-04
Method Of Making A Semiconductor Device With Embedded Stressor App 20080299724 - Grudowski; Paul A. ; et al.	2008-12-04
Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer App 20080258219 - Thean; Voon-Yew ; et al.	2008-10-23
Structure And Method For Strained Transistor Directly On Insulator App 20080237635 - Thean; Voon-Yew ; et al.	2008-10-02
Process of forming an electronic device including a semiconductor island over an insulating layer Grant 7,419,866 - Sadaka , et al. September 2, 2	2008-09-02
Process Of Forming An Electronic Device Including Forming A Gate Electrode Layer And Forming A Patterned Masking Layer App 20080188067 - Mathew; Leo ; et al.	2008-08-07
Selective Stress Relaxation By Amorphizing Implant In Strained Silicon On Insulator Integrated Circuit App 20080124858 - Nguyen; Bich-Yen ; et al.	2008-05-29
Method for forming vertical structures in a semiconductor device App 20080023803 - Shi; Zhonghai ; et al.	2008-01-31
Method of forming a FINFET structure Grant 7,323,389 - Goktepeli , et al. January 29, 2	2008-01-29
Twisted Dual-Substrate Orientation (DSO) Substrates App 20080020515 - White; Ted R. ; et al.	2008-01-24
Selective Uniaxial Stress Modification For Use With Strained Silicon On Insulator Integrated Circuit App 20080014688 - Thean; Voon-Yew ; et al.	2008-01-17
Method For Forming A Semiconductor Structure Having A Strained Silicon Layer App 20070277728 - Sadaka; Mariam G. ; et al.	2007-12-06
Engineering Strain In Thick Strained-soi Substrates App 20070281435 - Thean; Voon-Yew ; et al.	2007-12-06
Electronic Devices Including A Semiconductor Layer App 20070272952 - Thean; Voon-Yew ; et al.	2007-11-29
Selective Uniaxial Stress Relaxation By Layout Optimization In Strained Silicon On Insulator Integrated Circuit App 20070262385 - Nguyen; Bich-Yen ; et al.	2007-11-15
Hybrid Transistor Structure and a Method for Making the Same App 20070257322 - Shi; Zhonghai ; et al.	2007-11-08
Method to selectively form regions having differing properties and structure Grant 7,285,452 - Sadaka , et al. October 23, 2	2007-10-23
Integrated circuit with different channel materials for P and N channel transistors and method therefor App 20070241403 - Thean; Voon-Yew ; et al.	2007-10-18
Method of making a dual strained channel semiconductor device Grant 7,282,402 - Sadaka , et al. October 16, 2	2007-10-16
Method for making a semiconductor device with strain enhancement Grant 7,282,415 - Zhang , et al. October 16, 2	2007-10-16
Semiconductor Device Structure And Method Therefor App 20070235807 - White; Ted R. ; et al.	2007-10-11
Electronic device including semiconductor islands of different thicknesses over an insulating layer and a process of forming the same App 20070218707 - Sadaka; Mariam G. ; et al.	2007-09-20
Semiconductor Optical Devices And Method For Forming App 20070205421 - Mathew; Leo ; et al.	2007-09-06
Electronic devices including a semiconductor layer and a process for forming the same Grant 7,265,004 - Thean , et al. September 4, 2	2007-09-04
Method to selectively form regions having differing properties and structure App 20070190745 - Sadaka; Mariam G. ; et al.	2007-08-16
Graded semiconductor layer Grant 7,241,647 - Sadaka , et al. July 10, 2	2007-07-10
Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors Grant 7,235,502 - Kalpat , et al. June 26, 2	2007-06-26
Semiconductor transistor having structural elements of differing materials Grant 7,230,264 - Thean , et al. June 12, 2	2007-06-12
Semiconductor Optical Devices And Method For Forming App 20070126076 - Mathew; Leo ; et al.	2007-06-07
Semiconductor device structure and method therefor Grant 7,226,833 - White , et al. June 5, 2	2007-06-05
Transistor fabrication using double etch/refill process Grant 7,226,820 - Zhang , et al. June 5, 2	2007-06-05
Electronic devices including a semiconductor layer and a process for forming the same App 20070108481 - Thean; Voon-Yew ; et al.	2007-05-17
Method for forming a semiconductor structure and structure thereof App 20070099353 - Thean; Voon-Yew ; et al.	2007-05-03
Method for forming a semiconductor structure and structure thereof App 20070099361 - Thean; Voon-Yew ; et al.	2007-05-03
Method of forming a semiconductor device having a metal layer Grant 7,208,424 - Stephens , et al. April 24, 2	2007-04-24
Template layer formation Grant 7,208,357 - Sadaka , et al. April 24, 2	2007-04-24
Semiconductor structure having strained semiconductor and method therefor Grant 7,205,210 - Barr , et al. April 17, 2	2007-04-17
Method of forming a FINFET structure App 20070026615 - Goktepeli; Sinan ; et al.	2007-02-01
Channel orientation to enhance transistor performance Grant 7,160,769 - White , et al. January 9, 2	2007-01-09
Semiconductor device featuring an arched structure strained semiconductor layer App 20060226492 - Nguyen; Bich-Yen ; et al.	2006-10-12
Method of making a semiconductor device having an arched structure strained semiconductor layer App 20060228872 - Nguyen; Bich-Yen ; et al.	2006-10-12
Method of making a dual strained channel semiconductor device App 20060228851 - Sadaka; Mariam G. ; et al.	2006-10-12
Method for making a semiconductor device with strain enhancement App 20060228863 - Zhang; Da ; et al.	2006-10-12
Transistor fabrication using double etch/refill process App 20060228842 - Zhang; Da ; et al.	2006-10-12
Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors App 20060220157 - Kalpat; Sriram S. ; et al.	2006-10-05
Semiconductor optical devices and method for forming Grant 7,112,455 - Mathew , et al. September 26, 2	2006-09-26
Semiconductor fabrication process including recessed source/drain regions in an SOI wafer Grant 7,091,071 - Thean , et al. August 15, 2	2006-08-15
Asymmetric spacers and asymmetric source/drain extension layers App 20060170016 - Mathew; Leo ; et al.	2006-08-03
Semiconductor Fabrication Process Including Recessed Source/drain Regions In An Soi Wafer App 20060148196 - Thean; Voon-Yew ; et al.	2006-07-06
Double gate device having a heterojunction source/drain and strained channel Grant 7,067,868 - Thean , et al. June 27, 2	2006-06-27
Semiconductor layer formation Grant 7,056,778 - Liu , et al. June 6, 2	2006-06-06
Semiconductor device structure and method therefor App 20060094169 - White; Ted R. ; et al.	2006-05-04
Low RC product transistors in SOI semiconductor process Grant 7,037,795 - Barr , et al. May 2, 2	2006-05-02
Channel orientation to enhance transistor performance App 20060084207 - White; Ted R. ; et al.	2006-04-20
Low Rc Product Transistors In Soi Semiconductor Process App 20060084235 - Barr; Alexander L. ; et al.	2006-04-20
Method of manufacturing SOI template layer Grant 7,029,980 - Liu , et al. April 18, 2	2006-04-18
Semiconductor transistor having structural elements of differing materials App 20060076579 - Thean; Voon-Yew ; et al.	2006-04-13
Method For Forming A Semiconductor Device Having A Strained Channel And A Heterojunction Source/drain App 20060068553 - Thean; Voon-Yew ; et al.	2006-03-30
Double gate device having a heterojunction source/drain and strained channel App 20060065927 - Thean; Voon-Yew ; et al.	2006-03-30
Method for forming a semiconductor device having a strained channel and a heterojunction source/drain Grant 7,018,901 - Thean , et al. March 28, 2	2006-03-28
Method of forming a semiconductor device having a metal layer App 20060063364 - Stephens; Tab A. ; et al.	2006-03-23
Graded semiconductor layer App 20060040433 - Sadaka; Mariam G. ; et al.	2006-02-23
Strained semiconductor devices and method for forming at least a portion thereof App 20060030093 - Zhang; Da ; et al.	2006-02-09
Semiconductor transistor having structural elements of differing materials and method of formation Grant 6,979,622 - Thean , et al. December 27, 2	2005-12-27
Semiconductor optical devices and method for forming App 20050277211 - Mathew, Leo ; et al.	2005-12-15
Semiconductor structure having strained semiconductor and method therefor App 20050181549 - Barr, Alexander L. ; et al.	2005-08-18
SOI template layer App 20050070056 - Liu, Chun-Li ; et al.	2005-03-31
Template layer formation App 20050070053 - Sadaka, Mariam G. ; et al.	2005-03-31
Semiconductor layer formation App 20050070057 - Liu, Chun-Li ; et al.	2005-03-31

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.