loadpatents
name:-0.025666952133179
name:-0.024749994277954
name:-0.00057411193847656
Thayer; Larry J. Patent Filings

Thayer; Larry J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Thayer; Larry J..The latest application filed is for "memory system that utilizes a wide input/output (i/o) interface to interface memory storage with an interposer".

Company Profile
0.28.24
  • Thayer; Larry J. - Ft. Collins CO US
  • Thayer; Larry J. - Fort Collins CO
  • Thayer; Larry J - Fort Collins CO
  • Thayer; Larry J - Ft Collins CO
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Bit error rate reduction buffer, method and apparatus
Grant 9,298,668 - Thayer March 29, 2
2016-03-29
Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer
Grant 9,182,925 - Thayer November 10, 2
2015-11-10
Repairing high-speed serial links
Grant 8,914,683 - Thayer December 16, 2
2014-12-16
Memory module and method employing a multiplexer to replace a memory device
Grant 8,886,892 - Thayer November 11, 2
2014-11-11
Memory System That Utilizes A Wide Input/output (i/o) Interface To Interface Memory Storage With An Interposer
App 20140108683 - Thayer; Larry J.
2014-04-17
Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a method
Grant 8,634,221 - Thayer January 21, 2
2014-01-21
Systems and methods of selectively managing errors in memory modules
Grant 8,612,797 - Thayer , et al. December 17, 2
2013-12-17
High speed interface for dynamic random access memory (DRAM)
Grant 8,554,991 - Thayer October 8, 2
2013-10-08
A Memory System That Utilizes A Wide Input/output (i/o) Interface To Interface Memory Storage With An Interposer And That Utilizes A Serdes Interface To Interface A Memory Controller With An Integrated Circuit, And A Method
App 20130111123 - Thayer; Larry J.
2013-05-02
Memory controller
Grant 8,386,702 - Thayer , et al. February 26, 2
2013-02-26
System and method for distribution analysis of stacked-die integrated circuits
Grant 8,352,896 - Thayer January 8, 2
2013-01-08
System And Method For Distribution Analysis Of Stacked-die Integrated Circuits
App 20120221996 - Thayer; Larry J.
2012-08-30
High Speed Interface For Dynamic Random Access Memory (dram)
App 20120203961 - Thayer; Larry J.
2012-08-09
Defect management for a semiconductor memory system
Grant 7,996,710 - Nagaraj , et al. August 9, 2
2011-08-09
Error correction algorithm selection based upon memory organization
Grant 7,975,205 - Thayer July 5, 2
2011-07-05
System and method for implementing a stride value for memory testing
Grant 7,844,868 - Thayer , et al. November 30, 2
2010-11-30
Bit Error Rate Reduction Buffer, Method And Apparatus
App 20100275098 - Thayer; Larry J.
2010-10-28
Bit error rate reduction buffer
Grant 7,783,935 - Thayer August 24, 2
2010-08-24
System And Method For Implementing A Stride Value For Memory Testing
App 20100131810 - THAYER; LARRY J. ;   et al.
2010-05-27
Systems and methods for implementing a stride value for accessing memory
Grant 7,694,193 - Thayer , et al. April 6, 2
2010-04-06
Repairing High-speed Serial Links
App 20100083030 - Thayer; Larry J.
2010-04-01
Semiconductor memory device and system providing spare memory locations
Grant 7,656,727 - Thayer February 2, 2
2010-02-02
Storage element for mitigating soft errors in logic
Grant 7,539,931 - Thayer May 26, 2
2009-05-26
Semiconductor Memory Device And System Providing Spare Memory Locations
App 20080266999 - Thayer; Larry J.
2008-10-30
Defect Management For A Semiconductor Memory System
App 20080270675 - Nagaraj; Dheemanth ;   et al.
2008-10-30
Systems And Methods For Implementing A Stride Value For Accessing Memory
App 20080229035 - Thayer; Larry J. ;   et al.
2008-09-18
Memory Module And Method Employing A Multiplexer To Replace A Memory Device
App 20080181021 - Thayer; Larry J.
2008-07-31
Error Correction Algorithm Selection Based Upon Memory Organization
App 20080184093 - Thayer; Larry J.
2008-07-31
Memory System And Method For Storing And Correcting Data
App 20080077840 - Shaw; Mark ;   et al.
2008-03-27
Bit error rate reduction buffer
App 20070300104 - Thayer; Larry J.
2007-12-27
Systems and methods of selectively managing errors in memory modules
App 20070234112 - Thayer; Larry J. ;   et al.
2007-10-04
Memory controller
App 20070101094 - Thayer; Larry J. ;   et al.
2007-05-03
Determining hard errors vs. soft errors in memory
App 20070094569 - Thayer; Larry J. ;   et al.
2007-04-26
Power throttling system and method for a memory controller
App 20060248355 - Thayer; Larry J.
2006-11-02
Memory element for mitigating soft errors in logic
App 20060236158 - Thayer; Larry J.
2006-10-19
Storage element for mitigating soft errors in logic
App 20060227596 - Thayer; Larry J.
2006-10-12
Method and apparatus for performing a perspective projection in a graphics device of a computer graphics display system
Grant 6,940,525 - Hochmuth , et al. September 6, 2
2005-09-06
Content addressable memory with redundant stored data
App 20050027932 - Thayer, Larry J.
2005-02-03
Method and apparatus for performing a perspective projection in a graphics device of a computer graphics display system
App 20030011621 - Hochmuth, Roland M. ;   et al.
2003-01-16
System-wide texture offset addressing with page residence indicators for improved performance
Grant 6,362,824 - Thayer March 26, 2
2002-03-26
Method And Apparatus For Performing Perspective Projection In A Computer Graphics Display System
App 20010045958 - HOCHMUTH, ROLAND M. ;   et al.
2001-11-29
Polygon span interpolator with main memory Z buffer
Grant 5,493,644 - Thayer , et al. February 20, 1
1996-02-20
Polygon renderer which determines the coordinates of polygon edges to sub-pixel resolution in the X,Y and Z coordinates directions
Grant 5,278,949 - Thayer January 11, 1
1994-01-11
Graphics system with programmable tile size and multiplexed pixel data and partial pixel addresses based on tile size
Grant 4,965,751 - Thayer , et al. October 23, 1
1990-10-23

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed