Thatcher; Larry Edward

Patent Applications and Registrations

Patent applications and USPTO patent grants for Thatcher; Larry Edward.The latest application filed is for "system and method for multiple store buffer forwarding in a system with a restrictive memory model".

Company Profile

0.16.4

Thatcher; Larry Edward - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
TLB parity error recovery Grant 6,901,540 - Griffith, Jr. , et al. May 31, 2	2005-05-31
System and method for multiple store buffer forwarding in a system with a restrictive memory model App 20040019753 - Boatright, Bryan D. ; et al.	2004-01-29
System and method for multiple store buffer forwarding in a system with a restrictive memory model Grant 6,678,807 - Boatright , et al. January 13, 2	2004-01-13
Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline Grant 6,658,555 - Kahle , et al. December 2, 2	2003-12-02
System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model Grant 6,611,900 - Patel , et al. August 26, 2	2003-08-26
System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model App 20020199067 - Patel, Rajesh Bhikhubhai ; et al.	2002-12-26
Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing Grant 6,477,635 - Kahle , et al. November 5, 2	2002-11-05
System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model Grant 6,463,511 - Boatright , et al. October 8, 2	2002-10-08
System and method for multiple store buffer forwarding in a system with a restrictive memory model App 20020120813 - Boatright, Bryan D. ; et al.	2002-08-29
System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model App 20020087810 - Boatright, Bryan D. ; et al.	2002-07-04
System and method for invalidating an entry in a translation unit Grant 6,338,128 - Chang , et al. January 8, 2	2002-01-08
System and method for executing store instructions Grant 6,336,183 - Le , et al. January 1, 2	2002-01-01
System and method for merging multiple outstanding load miss instructions Grant 6,336,168 - Frederick, Jr. , et al. January 1, 2	2002-01-01
System and method for permitting out-of-order execution of load and store instructions Grant 6,301,654 - Ronchetti , et al. October 9, 2	2001-10-09
System and method for permitting out-of-order execution of load instructions Grant 6,266,768 - Frederick, Jr. , et al. July 24, 2	2001-07-24
Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor Grant 6,237,081 - Le , et al. May 22, 2	2001-05-22
Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching Grant 6,021,485 - Feiste , et al. February 1, 2	2000-02-01
Apparatus and method for processing multiple cache misses to a single cache line Grant 6,021,467 - Konigsburg , et al. February 1, 2	2000-02-01
Data processing system and method of operation having input/output drivers with reduced power consumption and noise levels Grant 5,974,259 - Casal , et al. October 26, 1	1999-10-26
Support for out-of-order execution of loads and stores in a processor Grant 5,931,957 - Konigsburg , et al. August 3, 1	1999-08-03

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