Tharmalingam; Kumara

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tharmalingam; Kumara.The latest application filed is for "search and retrieval of keyed data maintained using a keyed database".

Company Profile

0.22.8

Tharmalingam; Kumara - Los Gatos CA
Tharmalingam; Kumara - San Jose CA
Tharmalingam; Kumara - Santa Clara CA
Tharmalingam; Kumara - Mountain View CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Search and retrieval of keyed data maintained using a keyed database Grant 10,650,071 - Asgekar , et al.	2020-05-12
Search And Retrieval Of Keyed Data Maintained Using A Keyed Database App 20180150565 - Asgekar; Amogh S. ; et al.	2018-05-31
Transceiver system with reduced latency uncertainty Grant 9,559,881 - Carvalho , et al. January 31, 2	2017-01-31
Large multiplier for programmable logic device Grant 9,395,953 - Langhammer , et al. July 19, 2	2016-07-19
Flexible accumulator in digital signal processing circuitry Grant 9,170,775 - Zheng , et al. October 27, 2	2015-10-27
Large multiplier for programmable logic device Grant 9,063,870 - Langhammer , et al. June 23, 2	2015-06-23
Large Multiplier For Programmable Logic Device App 20140289293 - Langhammer; Martin ; et al.	2014-09-25
Large multiplier for programmable logic device Grant 8,788,562 - Langhammer , et al. July 22, 2	2014-07-22
Segmented clock network for transceiver array Grant 8,612,795 - Ding , et al. December 17, 2	2013-12-17
Large multiplier for programmable logic device Grant 8,386,553 - Langhammer , et al. February 26, 2	2013-02-26
Phase-locked loop architecture and clock distribution system Grant 8,228,102 - Pham , et al. July 24, 2	2012-07-24
Circuit design tools that support devices with real-time phase-locked loop reconfiguration capabilities Grant 8,171,443 - Chan , et al. May 1, 2	2012-05-01
Method and apparatus for compiling programmable logic device configurations Grant 8,001,537 - Iotov , et al. August 16, 2	2011-08-16
Large Multiplier For Programmable Logic Device App 20110161389 - Langhammer; Martin ; et al.	2011-06-30
Circuit design tools that support devices with real-time phase-locked loop reconfiguration capabilities Grant 7,949,980 - Chan , et al. May 24, 2	2011-05-24
Large multiplier for programmable logic device Grant 7,930,336 - Langhammer , et al. April 19, 2	2011-04-19
Flexible Accumulator In Digital Signal Processing Circuitry App 20100169404 - Zheng; Leon ; et al.	2010-07-01
Flexible accumulator in digital signal processing circuitry Grant 7,660,841 - Zheng , et al. February 9, 2	2010-02-09
Transceiver system with reduced latency uncertainty App 20090161738 - Carvalho; Neville ; et al.	2009-06-25
Clock distribution for specialized processing block in programmable logic device Grant 7,545,196 - Hutton , et al. June 9, 2	2009-06-09
Multiplier-accumulator block mode splitting Grant 7,437,401 - Zheng , et al. October 14, 2	2008-10-14
Large Multiplier For Programmable Logic Device App 20080133627 - Langhammer; Martin ; et al.	2008-06-05
Method for programming programmable logic device having specialized functional blocks Grant 7,082,592 - Tharmalingam July 25, 2	2006-07-25
Multiplier-accumulator block mode splitting App 20050187998 - Zheng, Leon ; et al.	2005-08-25
Flexible accumulator in digital signal processing circuitry App 20050187997 - Zheng, Leon ; et al.	2005-08-25

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