loadpatents
Patent applications and USPTO patent grants for Thareja; Gaurav.The latest application filed is for "integration of ferroelectric memory devices with transistors".
Patent | Date |
---|---|
Doped polar layers and semiconductor device incorporating same Grant 11,444,203 - Ramamoorthy , et al. September 13, 2 | 2022-09-13 |
Integration Of Ferroelectric Memory Devices With Transistors App 20220278116 - Manipatruni; Sasikanth ;   et al. | 2022-09-01 |
Ferroelectric capacitor and method of patterning such Grant 11,430,861 - Thareja , et al. August 30, 2 | 2022-08-30 |
Route anomaly detection and remediation Grant 11,418,429 - Chaturmohta , et al. August 16, 2 | 2022-08-16 |
Doped polar layers and semiconductor device incorporating same Grant 11,417,768 - Ramamoorthy , et al. August 16, 2 | 2022-08-16 |
Doped polar layers and semiconductor device incorporating same Grant 11,411,116 - Ramamoorthy , et al. August 9, 2 | 2022-08-09 |
Conformal High Concentration Boron Doping Of Semiconductors App 20220246432 - Gandikota; Srinivas ;   et al. | 2022-08-04 |
Doped polar layers and semiconductor device incorporating same Grant 11,398,570 - Ramamoorthy , et al. July 26, 2 | 2022-07-26 |
Low power ferroelectric based majority logic gate multiplier Grant 11,381,244 - Manipatruni , et al. July 5, 2 | 2022-07-05 |
Linear input and non-linear output threshold logic gate Grant 11,374,574 - Manipatruni , et al. June 28, 2 | 2022-06-28 |
Low Power Ferroelectric Based Majority Logic Gate Multiplier App 20220200600 - Manipatruni; Sasikanth ;   et al. | 2022-06-23 |
Integration Of A Ferroelectric Memory Device With A Transistor App 20220199633 - Thareja; Gaurav ;   et al. | 2022-06-23 |
Doped polar layers and semiconductor device incorporating same Grant 11,355,643 - Ramamoorthy , et al. June 7, 2 | 2022-06-07 |
Doped polar layers and semiconductor device incorporating same Grant 11,349,031 - Ramamoorthy , et al. May 31, 2 | 2022-05-31 |
Conformal high concentration boron doping of semiconductors Grant 11,328,928 - Gandikota , et al. May 10, 2 | 2022-05-10 |
Airgap Formation Processes App 20220115263 - Pal; Ashish ;   et al. | 2022-04-14 |
Low power ferroelectric based majority logic gate adder Grant 11,296,708 - Manipatruni , et al. April 5, 2 | 2022-04-05 |
Doped polar layers and semiconductor device incorporating same Grant 11,296,228 - Ramamoorthy , et al. April 5, 2 | 2022-04-05 |
Doped polar layers and semiconductor device incorporating same Grant 11,289,607 - Ramamoorthy , et al. March 29, 2 | 2022-03-29 |
Doped polar layers and semiconductor device incorporating same Grant 11,289,608 - Ramamoorthy , et al. March 29, 2 | 2022-03-29 |
Integration method of ferroelectric memory array Grant 11,289,497 - Thareja , et al. March 29, 2 | 2022-03-29 |
Method Of Fabricating A Semiconductor Device Having Reduced Contact Resistance App 20220093749 - THAREJA; Gaurav ;   et al. | 2022-03-24 |
Low power ferroelectric based majority logic gate carry propagate and serial adder Grant 11,283,453 - Manipatruni , et al. March 22, 2 | 2022-03-22 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20220077319 - Ramamoorthy; Ramesh ;   et al. | 2022-03-10 |
Self-aligned 3-d Epitaxial Structures For Mos Device Fabrication App 20220028747 - GLASS; Glenn A. ;   et al. | 2022-01-27 |
Methods And Apparatus For Metal Silicide Deposition App 20220005704 - LI; Xuebin ;   et al. | 2022-01-06 |
Methods And Apparatus For Metal Silicide Deposition App 20220005705 - LI; Xuebin ;   et al. | 2022-01-06 |
Airgap formation processes Grant 11,211,286 - Pal , et al. December 28, 2 | 2021-12-28 |
Method of fabricating a semiconductor device having reduced contact resistance Grant 11,195,923 - Thareja , et al. December 7, 2 | 2021-12-07 |
Self-aligned 3-D epitaxial structures for MOS device fabrication Grant 11,171,058 - Glass , et al. November 9, 2 | 2021-11-09 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210343872 - Ramamoorthy; Ramesh ;   et al. | 2021-11-04 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210343873 - Ramamoorthy; Ramesh ;   et al. | 2021-11-04 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210343871 - Ramamoorthy; Ramesh ;   et al. | 2021-11-04 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210343874 - Ramamoorthy; Ramesh ;   et al. | 2021-11-04 |
Doped polar layers and semiconductor device incorporating same Grant 11,164,976 - Ramamoorthy , et al. November 2, 2 | 2021-11-02 |
Majority logic gate based sequential circuit Grant 11,165,430 - Manipatruni , et al. November 2, 2 | 2021-11-02 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210328067 - Ramamoorthy; Ramesh ;   et al. | 2021-10-21 |
Methods and apparatus for metal silicide deposition Grant 11,152,221 - Li , et al. October 19, 2 | 2021-10-19 |
Semiconductor device, method of making a semiconductor device, and processing system Grant 11,152,479 - Thareja , et al. October 19, 2 | 2021-10-19 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210320211 - Ramamoorthy; Ramesh ;   et al. | 2021-10-14 |
Processing system and method of forming a contact Grant 11,114,320 - Thareja , et al. September 7, 2 | 2021-09-07 |
Gate Contact Over Active Regions App 20210249270 - THAREJA; Gaurav ;   et al. | 2021-08-12 |
Linear Input And Non-linear Output Threshold Logic Gate App 20210203325 - Manipatruni; Sasikanth ;   et al. | 2021-07-01 |
Pillar Capacitor And Method Of Fabricating Such App 20210202507 - Thareja; Gaurav ;   et al. | 2021-07-01 |
Ferroelectric Capacitor Integrated With Logic App 20210202690 - Thareja; Gaurav ;   et al. | 2021-07-01 |
Low Power Ferroelectric Based Majority Logic Gate Adder App 20210203324 - Manipatruni; Sasikanth ;   et al. | 2021-07-01 |
Method For Using And Forming Low Power Ferroelectric Based Majority Logic Gate Adder App 20210203326 - Manipatruni; Sasikanth ;   et al. | 2021-07-01 |
Integration Method Of Ferroelectric Memory Array App 20210202510 - Thareja; Gaurav ;   et al. | 2021-07-01 |
Ferroelectric Capacitor And Method Of Patterning Such App 20210202689 - Thareja; Gaurav ;   et al. | 2021-07-01 |
In-situ integrated chambers Grant 11,037,838 - Li , et al. June 15, 2 | 2021-06-15 |
Linear input and non-linear output threshold logic gate Grant 11,025,254 - Manipatruni , et al. June 1, 2 | 2021-06-01 |
Linear input and non-linear output majority logic gate Grant 11,018,672 - Manipatruni , et al. May 25, 2 | 2021-05-25 |
Linear input and non-linear output majority logic gate with and/or function Grant 11,012,076 - Manipatruni , et al. May 18, 2 | 2021-05-18 |
Gate contact over active processes Grant 11,004,687 - Thareja , et al. May 11, 2 | 2021-05-11 |
Route Anomaly Detection And Remediation App 20210135982 - CHATURMOHTA; Somesh ;   et al. | 2021-05-06 |
Majority logic gate fabrication Grant 10,951,213 - Manipatruni , et al. March 16, 2 | 2021-03-16 |
Low power ferroelectric based majority logic gate adder Grant 10,944,404 - Manipatruni , et al. March 9, 2 | 2021-03-09 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20200321472 - Ramamoorthy; Ramesh ;   et al. | 2020-10-08 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20200321344 - Ramamoorthy; Ramesh ;   et al. | 2020-10-08 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20200321473 - Ramamoorthy; Ramesh ;   et al. | 2020-10-08 |
Doped Polar Layers And Semiconductor Device Incorporating Same App 20200321474 - Ramamoorthy; Ramesh ;   et al. | 2020-10-08 |
Methods And Apparatus For Metal Silicide Deposition App 20200266068 - LI; Xuebin ;   et al. | 2020-08-20 |
Gate Contact Over Active Processes App 20200258744 - A1 | 2020-08-13 |
Semiconductor Device, Method Of Making A Semiconductor Device, And Processing System App 20200258997 - A1 | 2020-08-13 |
Processing System And Method Of Forming A Contact App 20200203481 - THAREJA; Gaurav ;   et al. | 2020-06-25 |
Method Of Fabricating A Semiconductor Device Having Reduced Contact Resistance App 20200203490 - THAREJA; Gaurav ;   et al. | 2020-06-25 |
Methods And Apparatus For Patterning Substrates Using Asymmetric Physical Vapor Deposition App 20200135464 - KESAPRAGADA; SREE RANGASAI V. ;   et al. | 2020-04-30 |
In-situ Integrated Chambers App 20200091010 - LI; Xuebin ;   et al. | 2020-03-19 |
Conformal High Concentration Boron Doping Of Semiconductors App 20190385851 - GANDIKOTA; SRINIVAS ;   et al. | 2019-12-19 |
Confined and scalable helmet Grant 10,410,867 - Sharma , et al. Sept | 2019-09-10 |
Airgap Formation Processes App 20190252239 - Pal; Ashish ;   et al. | 2019-08-15 |
Confined And Scalable Helmet App 20180315607 - Sharma; Vyom ;   et al. | 2018-11-01 |
Self-aligned 3-d Epitaxial Structures For Mos Device Fabrication App 20180019170 - GLASS; GLENN A. ;   et al. | 2018-01-18 |
Self-aligned 3-D epitaxial structures for MOS device fabrication Grant 9,728,464 - Glass , et al. August 8, 2 | 2017-08-08 |
Conversion Of Thin Transistor Elements From Silicon To Silicon Germanium App 20150115216 - Glass; Glenn A. ;   et al. | 2015-04-30 |
Conversion of thin transistor elements from silicon to silicon germanium Grant 8,957,476 - Glass , et al. February 17, 2 | 2015-02-17 |
Conversion Of Thin Transistor Elements From Silicon To Silicon Germanium App 20140175543 - Glass; Glenn A. ;   et al. | 2014-06-26 |
Self-aligned 3-d Epitaxial Structures For Mos Device Fabrication App 20140027860 - Glass; Glenn A. ;   et al. | 2014-01-30 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.