Thambidurai Karthik

USPTO Trademark & Patent Filings

Trademark applications and grants for Thambidurai Karthik. Thambidurai Karthik has 1 trademark applications. The latest application filed is for "CHENNAI CAFE"

Company Profile

Karthik Thambidurai
karthik thambidurai
Thambidurai; Karthik - Plano TX

Trademarks Patents

Patent Applications

Patent Application	Date
THREE-DIMENSIONAL CHIP-TO-WAFER INTEGRATION 20160071826 - 14/942708 Kelkar; Amit S. ; et al.	2016-03-10
WAFER LEVEL DEVICE AND METHOD WITH CANTILEVER PILLAR STRUCTURE 20150279799 - 14/492576 Thambidurai; Karthik ; et al.	2015-10-01
TECHNIQUE FOR WAFER-LEVEL PROCESSING OF QFN PACKAGES 20150028475 - 14/512506 Khandekar; Viren ; et al.	2015-01-29
WAFER-LEVEL CHIP-SCALE PACKAGE DEVICE HAVING BUMP ASSEMBLIES CONFIGURED TO FURNISH SHOCK ABSORBER FUNCTIONALITY 20150008576 - 14/195946 Khandekar; Viren ; et al.	2015-01-08
LOW-COST LOW-PROFILE SOLDER BUMP PROCESS FOR ENABLING ULTRA-THIN WAFER-LEVEL PACKAGING (WLP) PACKAGES 20140167252 - 13/718130 Thambidurai; Karthik ; et al.	2014-06-19
Wafer-level chip-scale package device having bump assemblies configured to maintain standoff height 10,804,233 - 13/287,254 Khandekar , et al. October 13, 2	2020-10-13
Wafer-level chip-scale package device having bump assemblies configured to maintain standoff height 10,804,233 - 13/287,254 Khandekar , et al. October 13, 2	2020-10-13
Wafer level package device formed using a wafer level lead frame on a carrier wafer having a similar coefficient of thermal expansion as an active wafer 10,304,758 - 13/788,291 Thambidurai , et al.	2019-05-28
Three-dimensional chip-to-wafer integration 10,032,749 - 14/942,708 Kelkar , et al. July 24, 2	2018-07-24
Wafer level device and method with cantilever pillar structure 9,806,047 - 14/492,576 Thambidurai , et al. October 31, 2	2017-10-31

Patent Grants & Applications

Trademark Applications

Mark Image Registration \| Serial	Trademark Application Date
"CHENNAI CAFE" 4599991 86034618	CHENNAI CAFE 2013-08-11

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