Teraoka; Eiichi
Patent Applications and Registrations
Patent applications and USPTO patent grants for Teraoka; Eiichi.The latest application filed is for "mos integrated circuit device operating with low power consumption".
- Teraoka; Eiichi - Hyogo JP
- Teraoka; Eiichi - Itami JP
| Patent | Date |
|---|---|
| MOS integrated circuit device operating with low power consumption Grant 6,333,571 - Teraoka , et al. December 25, 2 | 2001-12-25 |
| MOS integrated circuit device operating with low power consumption Grant 6,097,113 - Teraoka , et al. August 1, 2 | 2000-08-01 |
| Microprocessor having built-in synchronous memory with power-saving feature Grant 5,276,889 - Shiraishi , et al. January 4, 1 | 1994-01-04 |
| Decimating digital finite impulse response filter Grant 5,191,547 - Kawamoto , et al. March 2, 1 | 1993-03-02 |
| Semiconductor integrated circuit with master and slave latches Grant 5,162,667 - Yasui , et al. November 10, 1 | 1992-11-10 |
| Synchronous static random access memory having precharge system and operating method thereof Grant 4,856,106 - Teraoka August 8, 1 | 1989-08-08 |
| Semiconductor memory device having initialization transistor Grant 4,777,623 - Shimazu , et al. October 11, 1 | 1988-10-11 |
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