Terano; Toshio

Patent Applications and Registrations

Patent applications and USPTO patent grants for Terano; Toshio.The latest application filed is for "semiconductor integrated circuit".

Company Profile

0.15.14

Terano; Toshio - Osaka N/A JP
Terano; Toshio - Kanagawa JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor integrated circuit Grant 8,520,463 - Sumitani , et al. August 27, 2	2013-08-27
Semiconductor memory device Grant 8,345,470 - Satomi , et al. January 1, 2	2013-01-01
Semiconductor Integrated Circuit App 20120155211 - SUMITANI; NORIHIKO ; et al.	2012-06-21
Semiconductor memory device Grant 8,077,530 - Ishikura , et al. December 13, 2	2011-12-13
Semiconductor Memory Device App 20110188327 - ISHIKURA; Satoshi ; et al.	2011-08-04
Semiconductor memory device Grant 7,948,787 - Ishikura , et al. May 24, 2	2011-05-24
Semiconductor Memory Device App 20110103126 - SATOMI; Katsuji ; et al.	2011-05-05
Semiconductor memory device Grant 7,872,893 - Kurumada , et al. January 18, 2	2011-01-18
Semiconductor Memory Device App 20110007575 - ISHIKURA; Satoshi ; et al.	2011-01-13
Semiconductor memory device Grant 7,839,697 - Ishikura , et al. November 23, 2	2010-11-23
Semiconductor integrated circuit Grant 7,692,955 - Terada , et al. April 6, 2	2010-04-06
Non-volatile semiconductor memory device Grant 7,453,118 - Tomiie , et al. November 18, 2	2008-11-18
Semiconductor Integrated Circuit App 20080253171 - Terada; Yutaka ; et al.	2008-10-16
Semiconductor Memory Device App 20080151606 - KURUMADA; Marefusa ; et al.	2008-06-26
Semiconductor Memory Device App 20080151653 - ISHIKURA; Satoshi ; et al.	2008-06-26
Semiconductor device and method of producing the same Grant 7,227,255 - Nomoto , et al. June 5, 2	2007-06-05
Method of fabricating a memory transistor array utilizing insulated word lines as gate electrodes Grant 7,049,180 - Nomoto , et al. May 23, 2	2006-05-23
Memory transistor array utilizing insulated word lines as gate electrodes Grant 7,023,061 - Nomoto , et al. April 4, 2	2006-04-04
Memory transistor array utilizing insulated word lines as gate electrodes Grant 7,012,329 - Nomoto , et al. March 14, 2	2006-03-14
Semiconductor device and method of producing the same App 20050255652 - Nomoto, Kazumasa ; et al.	2005-11-17
Semiconductor device and method of producing the same App 20050218522 - Nomoto, Kazumasa ; et al.	2005-10-06
Semiconductor device and method of producing the same App 20050189570 - Nomoto, Kazumasa ; et al.	2005-09-01
Non-volatile semiconductor memory device App 20050161701 - Tomiie, Hideto ; et al.	2005-07-28
Semiconductor device and method of producing the same App 20050146015 - Nomoto, Kazumasa ; et al.	2005-07-07
Nonvolatile semiconductor memory device Grant 6,911,691 - Tomiie , et al. June 28, 2	2005-06-28
Semiconductor device and method of producing the same Grant 6,891,262 - Nomoto , et al. May 10, 2	2005-05-10
Nonvolatile semiconductor memory App 20040026733 - Tomiie, Hideto ; et al.	2004-02-12
Semiconductor device and method of producing the same App 20030025147 - Nomoto, Kazumasa ; et al.	2003-02-06

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