Teramoto; Youji

Patent Applications and Registrations

Patent applications and USPTO patent grants for Teramoto; Youji.The latest application filed is for "reformed sic wafer manufacturing method, epitaxial layer-attached sic wafer, method for manufacturing same, and surface processi".

Company Profile

3.3.6

Teramoto; Youji - Kanonji JP
Teramoto; Youji - Kanonji-shi JP
TERAMOTO; Youji - Hiroshima-shi JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for manufacturing reformed sic wafer, epitaxial layer-attached sic wafer, method for manufacturing same, and surface treatment method Grant 11,261,539 - Torimi , et al. March 1, 2	2022-03-01
Surface treatment method for SiC substrate Grant 10,665,465 - Kaneko , et al.	2020-05-26
Reformed Sic Wafer Manufacturing Method, Epitaxial Layer-attached Sic Wafer, Method For Manufacturing Same, And Surface Processi App 20200095703 - Torimi; Satoshi ; et al.	2020-03-26
Etching method for SiC substrate and holding container Grant 10,388,536 - Torimi , et al. A	2019-08-20
METHOD FOR MANUFACTURING THIN SiC WAFER AND THIN SiC WAFER App 20180069084 - TORIMI; SATOSHI ; et al.	2018-03-08
SURFACE TREATMENT METHOD FOR SiC SUBSTRATE App 20170345672 - Kaneko; Tadaaki ; et al.	2017-11-30
Etching Method For Sic Substrate And Holding Container App 20170323797 - Torimi; Satoshi ; et al.	2017-11-09
METHOD FOR MANUFACTURING THIN SiC WAFER AND THIN SiC WAFER App 20170236905 - Torimi; Satoshi ; et al.	2017-08-17
Strip Crossbow Reduction And Strip Vibration Reduction Method And Hot Dip Coated Strip Manufacturing Method Using The Strip Stabilization Method App 20090191360 - TERAMOTO; Youji ; et al.	2009-07-30

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