loadpatents
Patent applications and USPTO patent grants for Tepolt; Gary B..The latest application filed is for "method and apparatus for forming multi-layered vias in sequentially fabricated circuits".
Patent | Date |
---|---|
Method and apparatus for forming multi-layered vias in sequentially fabricated circuits Grant 10,453,787 - Karpman , et al. Oc | 2019-10-22 |
Electronic module subassemblies Grant 9,693,469 - Tepolt , et al. June 27, 2 | 2017-06-27 |
Method And Apparatus For Forming Multi-layered Vias In Sequentially Fabricated Circuits App 20160343652 - Karpman; Maurice S. ;   et al. | 2016-11-24 |
Electronic modules Grant 9,425,069 - Racz , et al. August 23, 2 | 2016-08-23 |
Electronic Module Subassemblies And Methods For Fabricating The Same App 20150181709 - Tepolt; Gary B. ;   et al. | 2015-06-25 |
Electronic Modules App 20130329376 - Racz; Livia M. ;   et al. | 2013-12-12 |
Electronic modules and methods for forming the same Grant 8,535,984 - Racz , et al. September 17, 2 | 2013-09-17 |
Interposers, electronic modules, and methods for forming the same Grant 8,273,603 - Racz , et al. September 25, 2 | 2012-09-25 |
Interposers, Electronic Modules, And Methods For Forming The Same App 20120086135 - Thompson; Jeffrey C. ;   et al. | 2012-04-12 |
Electronic Modules and Methods for Forming the Same App 20110309528 - Racz; Livia M. ;   et al. | 2011-12-22 |
Electronic modules and methods for forming the same Grant 8,017,451 - Racz , et al. September 13, 2 | 2011-09-13 |
Removal of integrated circuits from packages Grant 7,981,698 - Pryputniewicz , et al. July 19, 2 | 2011-07-19 |
Die thinning processes and structures Grant 7,960,247 - Thompson , et al. June 14, 2 | 2011-06-14 |
Die Thinning Processes And Structures App 20090251879 - Thompson; Jeffrey C. ;   et al. | 2009-10-08 |
Electronic Modules and Methods for Forming the Same App 20090250823 - Racz; Livia M. ;   et al. | 2009-10-08 |
Interposers, Electronic Modules, And Methods For Forming The Same App 20090250249 - Racz; Livia M. ;   et al. | 2009-10-08 |
Removal of integrated circuits from packages App 20080217773 - Pryputniewicz; Dariusz R. ;   et al. | 2008-09-11 |
Robotic wafer handler Grant 5,746,565 - Tepolt May 5, 1 | 1998-05-05 |
Process chamber for semiconductor substrates Grant 5,611,886 - Bachman , et al. March 18, 1 | 1997-03-18 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.