Tellez; Gustavo Enrique

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tellez; Gustavo Enrique.The latest application filed is for "multi-cycle latch tree synthesis".

Company Profile

5.10.7

Tellez; Gustavo Enrique - Hyde Park NY
Tellez; Gustavo Enrique - Essex Junction VT
Tellez; Gustavo Enrique - Cornwall on Hudson NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Generation and selection of universally routable via mesh specifications in an integrated circuit Grant 11,341,311 - Koone , et al. May 24, 2	2022-05-24
Dynamic SADP region generation Grant 11,087,062 - Xiang , et al. August 10, 2	2021-08-10
Multi-cycle latch tree synthesis Grant 11,074,379 - Reddy , et al. July 27, 2	2021-07-27
Autonomous placement to satisfy self-aligned double patterning constraints Grant 10,796,064 - Xiang , et al. October 6, 2	2020-10-06
Multi-cycle Latch Tree Synthesis App 20200311221 - Reddy; Lakshmi N. ; et al.	2020-10-01
Identification of hotspots in congestion analysis during physical design of integrated circuit Grant 10,747,935 - Li , et al. A	2020-08-18
Triple and quad coloring of shape layouts Grant 10,719,656 - Lvov , et al.	2020-07-21
Identification Of Hotspots In Congestion Analysis During Physical Design Of Integrated Circuit App 20200218789 - Li; Zhichao ; et al.	2020-07-09
Triple and quad coloring of shape layouts Grant 10,606,978 - Lvov , et al.	2020-03-31
Autonomous Placement To Satisfy Self-aligned Double Patterning Constraints App 20200057836 - Xiang; Hua ; et al.	2020-02-20
Triple And Quad Coloring Of Shape Layouts App 20190197215 - Lvov; Alexey Y. ; et al.	2019-06-27
Triple and quad coloring shape layouts Grant 10,223,496 - Lvov , et al.	2019-03-05
Triple And Quad Coloring Of Shape Layouts App 20180144089 - Lvov; Alexey Y. ; et al.	2018-05-24
Triple And Quad Coloring Of Shape Layouts App 20180144088 - Lvov; Alexey Y. ; et al.	2018-05-24
Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories Grant 6,993,692 - Ouellette , et al. January 31, 2	2006-01-31
Method, System And Apparatus For Aggregating Failures Across Multiple Memories And Applying A Common Defect Repair Solution To All Of The Multiple Memories App 20040268198 - Ouellette, Michael R. ; et al.	2004-12-30
Incremental method for critical area and critical region computation of via blocks Grant 6,247,853 - Papadopoulou , et al. June 19, 2	2001-06-19

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