Tellez; Gustavo E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tellez; Gustavo E..The latest application filed is for "self-aligned double patterning-aware routing in chip manufacturing".

Company Profile

14.34.31

Tellez; Gustavo E. - Hyde Park NY
Tellez; Gustavo E - Essex Junction VT
Tellez; Gustavo E. - Essex Junction VT
Tellez; Gustavo E. - Essex Junciton VT
Tellez; Gustavo E. - Cornwall on Hudson NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
White space insertion for enhanced routability Grant 11,120,192 - Xiang , et al. September 14, 2	2021-09-14
Capacity model for global routing Grant 10,831,972 - Pandey , et al. November 10, 2	2020-11-10
Self-aligned double patterning-aware routing in chip manufacturing Grant 10,726,187 - Pandey , et al.	2020-07-28
Self-aligned Double Patterning-aware Routing In Chip Manufacturing App 20200104449 - Pandey; Diwesh ; et al.	2020-04-02
Engineering change order aware global routing Grant 10,606,976 - Kazda , et al.	2020-03-31
Capacity Model For Global Routing App 20200057835 - Pandey; Diwesh ; et al.	2020-02-20
Integrated circuit buffering solutions considering sink delays Grant 10,503,841 - Zhou , et al. Dec	2019-12-10
Integrated circuit buffering solutions considering sink delays Grant 10,496,764 - Zhou , et al. De	2019-12-03
Integrated Circuit Buffering Solutions Considering Sink Delays App 20190278873 - Zhou; Ying ; et al.	2019-09-12
Integrated Circuit Buffering Solutions Considering Sink Delays App 20190278874 - Zhou; Ying ; et al.	2019-09-12
Integrated circuit buffering solutions considering sink delays Grant 10,372,837 - Zhou , et al.	2019-08-06
Integrated circuit buffering solutions considering sink delays Grant 10,372,836 - Zhou , et al.	2019-08-06
Integrated circuit buffering solutions considering sink delays Grant 10,346,558 - Zhou , et al. July 9, 2	2019-07-09
Capacity Model For Global Routing App 20190138683 - Pandey; Diwesh ; et al.	2019-05-09
Capacity model for global routing Grant 10,229,239 - Pandey , et al.	2019-03-12
Integrated Circuit Buffering Solutions Considering Sink Delays App 20180373814 - Zhou; Ying ; et al.	2018-12-27
Integrated Circuit Buffering Solutions Considering Sink Delays App 20180373813 - Zhou; Ying ; et al.	2018-12-27
Integrated Circuit Buffering Solutions Considering Sink Delays App 20180373815 - Zhou; Ying ; et al.	2018-12-27
Capacity Model For Global Routing App 20180285508 - Pandey; Diwesh ; et al.	2018-10-04
Engineering Change Order Aware Global Routing App 20180285507 - Kazda; Michael A. ; et al.	2018-10-04
Orthogonal circuit element routing Grant 9,245,076 - Gerousis , et al. January 26, 2	2016-01-26
Reducing color conflicts in triple patterning lithography Grant 9,158,885 - Gray , et al. October 13, 2	2015-10-13
Timing driven routing for noise reduction in integrated circuit design Grant 8,938,702 - Hogan , et al. January 20, 2	2015-01-20
Orthogonal Circuit Element Routing App 20140359548 - Gerousis; Vassilios ; et al.	2014-12-04
Via selection in integrated circuit design Grant 8,631,375 - Arelt , et al. January 14, 2	2014-01-14
Via Selection In Integrated Circuit Design App 20130268908 - Arelt; Robert R. ; et al.	2013-10-10
Method to reduce delay variation by sensitivity cancellation Grant 8,448,110 - Habitz , et al. May 21, 2	2013-05-21
Detailed routability by cell placement Grant 8,347,257 - Alpert , et al. January 1, 2	2013-01-01
Method for IC wiring yield optimization, including wire widening during and after routing Grant 8,230,378 - Cohn , et al. July 24, 2	2012-07-24
Detailed Routability By Cell Placement App 20110302545 - Alpert; Charles J. ; et al.	2011-12-08
Method and apparatus for manufacturing diamond shaped chips Grant 7,961,932 - Allen , et al. June 14, 2	2011-06-14
Method To Reduce Delay Variation By Sensitivity Cancellation App 20110126163 - Habitz; Peter A. ; et al.	2011-05-26
Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning Grant 7,895,545 - Cohn , et al. February 22, 2	2011-02-22
Systematic yield in semiconductor manufacture Grant 7,725,864 - Bergeron , et al. May 25, 2	2010-05-25
Systematic yield in semiconductor manufacture Grant 7,721,240 - Bergeron , et al. May 18, 2	2010-05-18
Method for IC wiring yield optimization, including wire widening during and after routing Grant 7,657,859 - Cohn , et al. February 2, 2	2010-02-02
Method For Ic Wiring Yield Optimization, Including Wire Widening During And After Routing App 20100023913 - Cohn; John M. ; et al.	2010-01-28
Methods For Designing A Product Chip A Priori For Design Subsetting, Feature Analysis, And Yield Learning App 20090259983 - Cohn; John M. ; et al.	2009-10-15
Systematic Yield In Semiconductor Manufacture App 20080104568 - BERGERON; Paul H. ; et al.	2008-05-01
Systematic Yield In Semiconductor Manufacture App 20080059918 - Bergeron; Paul H. ; et al.	2008-03-06
Systematic yield in semiconductor manufacture Grant 7,337,415 - Bergeron , et al. February 26, 2	2008-02-26
Method And Apparatus For Manufacturing Diamond Shaped Chips App 20080018872 - Allen; Robert J. ; et al.	2008-01-24
Method and apparatus for manufacturing diamond shaped chips Grant 7,289,659 - Allen , et al. October 30, 2	2007-10-30
A Method For Ic Wiring Yield Optimization, Including Wire Widening During And After Routing App 20070136714 - Cohn; John M. ; et al.	2007-06-14
Circuit area minimization using scaling Grant 7,117,456 - Gray , et al. October 3, 2	2006-10-03
Method and system for improving integrated circuit manufacturing productivity Grant 7,076,749 - Kemerer , et al. July 11, 2	2006-07-11
Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization Grant 7,062,729 - Gray , et al. June 13, 2	2006-06-13
Improving Systematic Yield In Semiconductor Manufacture App 20060085769 - Bergeron; Paul H. ; et al.	2006-04-20
Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization App 20060064661 - Gray; Michael S. ; et al.	2006-03-23
Practical method for hierarchical-preserving layout optimization of integrated circuit layout Grant 6,986,109 - Allen , et al. January 10, 2	2006-01-10
Method And System For Improving Integrated Circuit Manufacturing Productivity App 20050278663 - Kemerer, Douglas W. ; et al.	2005-12-15
Use of a layout-optimization tool to increase the yield and reliability of VLSI designs Grant 6,941,528 - Allen , et al. September 6, 2	2005-09-06
Circuit Area Minimization Using Scaling App 20050125748 - Gray, Michael S. ; et al.	2005-06-09
Method for improving chip yields in the presence of via flaring Grant 6,904,575 - Allen , et al. June 7, 2	2005-06-07
The Use Of A Layout-optimization Tool To Increase The Yield And Reliability Of Vlsi Designs App 20050048677 - Allen, Robert J. ; et al.	2005-03-03
The Use Of A Layout-optimization Tool To Increase The Yield And Reliability Of Vlsi Designs App 20050050500 - Allen, Robert J. ; et al.	2005-03-03
The Use Of A Layout-optimization Tool To Increase The Yield And Reliability Of Vlsi Designs App 20050050501 - Allen, Robert J. ; et al.	2005-03-03
Method And Apparatus For Manufacturing Diamond Shaped Chips App 20040258294 - Allen, Robert J. ; et al.	2004-12-23
Practical method for hierarchical-preserving layout optimization of integrated circuit layout App 20040230922 - Allen, Robert J. ; et al.	2004-11-18
Method for prediction random defect yields of integrated circuits with accuracy and computation time controls Grant 6,738,954 - Allen , et al. May 18, 2	2004-05-18
Method for improving chip yields in the presence of via flaring App 20030229866 - Allen, Robert J. ; et al.	2003-12-11
Design rule correction system and method Grant 6,189,132 - Heng , et al. February 13, 2	2001-02-13