| Patent | Date |
|---|
Operand pool instruction reservation clustering in a scheduler circuit in a processor
Grant 11,392,410 - Priyadarshi , et al. July 19, 2 | 2022-07-19 |
Opportunistic consumer instruction steering based on producer instruction value prediction in a multi-cluster processor
Grant 11,327,763 - Perais , et al. May 10, 2 | 2022-05-10 |
Opportunistic Consumer Instruction Steering Based On Producer Instruction Value Prediction In A Multi-cluster Processor
App 20210389951 - PERAIS; Arthur ; et al. | 2021-12-16 |
Operand Pool Instruction Reservation Clustering In A Scheduler Circuit In A Processor
App 20210318905 - PRIYADARSHI; Shivam ; et al. | 2021-10-14 |
Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)
Grant 11,113,068 - Tekmen , et al. September 7, 2 | 2021-09-07 |
Reach Matrix Scheduler Circuit For Scheduling Of Instructions To Be Executed In A Processor
App 20210216327 - TEKMEN; Yusuf Cagatay ; et al. | 2021-07-15 |
Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processor
Grant 11,061,677 - Seth , et al. July 13, 2 | 2021-07-13 |
Latency-based instruction reservation station clustering in a scheduler circuit in a processor
Grant 11,023,243 - Tekmen , et al. June 1, 2 | 2021-06-01 |
Operand-based reach explicit dataflow processors, and related methods and computer-readable media
Grant 10,956,162 - Clancy , et al. March 23, 2 | 2021-03-23 |
Latency-based Instruction Reservation Clustering In A Scheduler Circuit In A Processor
App 20210026639 - TEKMEN; Yusuf Cagatay ; et al. | 2021-01-28 |
Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices
Grant 10,896,041 - Priyadarshi , et al. January 19, 2 | 2021-01-19 |
Operand-based Reach Explicit Dataflow Processors, And Related Methods And Computer-readable Media
App 20200409712 - CLANCY; Robert Douglas ; et al. | 2020-12-31 |
Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processor
Grant 10,877,768 - Priyadarshi , et al. December 29, 2 | 2020-12-29 |
Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture
Grant 10,860,328 - Priyadarshi , et al. December 8, 2 | 2020-12-08 |
Providing Late Physical Register Allocation And Early Physical Register Release In Out-of-order Processor (oop)-based Devices Im
App 20200097296 - Priyadarshi; Shivam ; et al. | 2020-03-26 |
Combining Load Or Store Instructions
App 20200004550 - THAKKER; Harsh ; et al. | 2020-01-02 |
Fast reuse of physical register names
Grant 10,514,921 - Talluru , et al. Dec | 2019-12-24 |
Method, Apparatus, And System For Reducing Live Readiness Calculations In Reservation Stations
App 20190332385 - SMITH; Rodney Wayne ; et al. | 2019-10-31 |
Providing Early Pipeline Optimization Of Conditional Instructions In Processor-based Systems
App 20190294443 - Navada; Sandeep Suresh ; et al. | 2019-09-26 |
Fast Reuse Of Physical Register Names
App 20190073218 - TALLURU; Tejaswi ; et al. | 2019-03-07 |
High Performance Recovery From Misspeculation Of Load Latency
App 20170046164 - MADHAVAN; Raghavan ; et al. | 2017-02-16 |
Efficient Handling Of Register Files
App 20170046160 - SETH; Kiran Ravi ; et al. | 2017-02-16 |
Processor with a coprocessor having early access to not-yet issued instructions
Grant 9,304,774 - Dockser , et al. April 5, 2 | 2016-04-05 |
Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is available
Grant 9,164,772 - Dockser , et al. October 20, 2 | 2015-10-20 |
Processor with Hazard Tracking Employing Register Range Compares
App 20130173886 - Dockser; Kenneth Alan ; et al. | 2013-07-04 |
Processor with a Hybrid Instruction Queue
App 20120204004 - Dockser; Kenneth Alan ; et al. | 2012-08-09 |
Processor with a Hybrid Instruction Queue with Instruction Elaboration Between Sections
App 20120204008 - Dockser; Kenneth Alan ; et al. | 2012-08-09 |
Processor with a Coprocessor having Early Access to Not-Yet Issued Instructions
App 20120204005 - Dockser; Kenneth Alan ; et al. | 2012-08-09 |
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