Tehrani; Peivand

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tehrani; Peivand.The latest application filed is for "analyzing delay variations and transition time variations for electronic circuits".

Company Profile

1.11.9

Tehrani; Peivand - Campbell CA
Tehrani; Peivand - Mountain View CA
Tehrani; Peivand - Camirillo CA
Tehrani; Peivand - Camarillo CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Analyzing delay variations and transition time variations for electronic circuits Grant 11,288,426 - Huynh , et al. March 29, 2	2022-03-29
Method and apparatus for reducing pessimism of graph based static timing analysis Grant 11,222,155 - Tehrani , et al. January 11, 2	2022-01-11
Analyzing Delay Variations and Transition Time Variations for Electronic Circuits App 20200410151 - Huynh; Duc ; et al.	2020-12-31
Analyzing delay variations and transition time variations for electronic circuits Grant 10,783,301 - Huynh , et al. Sept	2020-09-22
Analyzing Delay Variations and Transition Time Variations for Electronic Circuits App 20190197212 - Huynh; Duc ; et al.	2019-06-27
Analyzing delay variations and transition time variations for electronic circuits Grant 10,255,395 - Huynh , et al.	2019-04-09
Analyzing Delay Variations and Transition Time Variations for Electronic Circuits App 20170262569 - Huynh; Duc ; et al.	2017-09-14
Arrival edge usage in timing analysis Grant 9,026,965 - Mogal , et al. May 5, 2	2015-05-05
Arrival Edge Usage In Timing Analysis App 20140282317 - Mogal; Hushrav Darabshah ; et al.	2014-09-18
Consistent hierarchical timing model with crosstalk consideration Grant 8,468,479 - Tehrani , et al. June 18, 2	2013-06-18
Crosstalk time-delay analysis using random variables Grant 8,341,574 - Gandikota , et al. December 25, 2	2012-12-25
Determining an order for visiting circuit blocks in a circuit design for fixing design requirement violations Grant 8,336,013 - Oh , et al. December 18, 2	2012-12-18
Consistent Hierarchical Timing Model with Crosstalk Consideration App 20120239371 - Tehrani; Peivand ; et al.	2012-09-20
Variation aware victim and aggressor timing overlap detection by pessimism reduction based on relative positions of timing windows Grant 8,219,952 - Tehrani , et al. July 10, 2	2012-07-10
Determining An Order For Visiting Circuit Blocks In A Circuit Design For Fixing Design Requirement Violations App 20110185335 - Oh; Nahmsuk ; et al.	2011-07-28
Distorted waveform propagation and crosstalk delay analysis using multiple cell models Grant 7,861,198 - Ding , et al. December 28, 2	2010-12-28
Crosstalk Time-delay Analysis Using Random Variables App 20100229136 - Gandikota; Ravikishore ; et al.	2010-09-09
Variation Aware Victim And Aggressor Timing Overlap Detection By Pessimism Reduction Based On Relative Positions Of Timing Windows App 20100218152 - Tehrani; Peivand ; et al.	2010-08-26
Distorted Waveform Propagation and Crosstalk Delay Analysis Using Multiple Cell Models App 20090089729 - Ding; Li ; et al.	2009-04-02

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