Teh; Young Way

Patent Applications and Registrations

Patent applications and USPTO patent grants for Teh; Young Way.The latest application filed is for "semiconductor device with an oversized local contact as a faraday shield".

Company Profile

0.30.28

Teh; Young Way - Wappingers Falls NY US
Teh; Young Way - Wappinger Falls NY
Teh; Young Way - Singapore N/A SG
Teh; Young Way - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High-K metal gate device Grant 8,853,796 - Teh , et al. October 7, 2	2014-10-07
Semiconductor device with an oversized local contact as a Faraday shield Grant 8,664,717 - Liu , et al. March 4, 2	2014-03-04
Spacer-less low-K dielectric processes Grant 8,624,329 - Lee , et al. January 7, 2	2014-01-07
Integrated circuit structure having substantially planar N-P step height and methods of forming Grant 8,563,394 - Li , et al. October 22, 2	2013-10-22
Poly profile engineering to modulate spacer induced stress for device enhancement Grant 8,519,445 - Ho , et al. August 27, 2	2013-08-27
Semiconductor Device With an Oversized Local Contact as a Faraday Shield App 20130175617 - Liu; Yanxiang ; et al.	2013-07-11
Spacer and process to enhance the strain in the channel with stress liner Grant 8,461,009 - Ajmera , et al. June 11, 2	2013-06-11
High-k Metal Gate Device App 20120292719 - TEH; Young Way ; et al.	2012-11-22
Integrated Circuit Structure Having Substantially Planar N-p Step Height And Methods Of Forming App 20120256268 - Li; Weipeng ; et al.	2012-10-11
Balancing NFET and PFET performance using straining layers Grant 8,106,462 - Chen , et al. January 31, 2	2012-01-31
Poly Profile Engineering To Modulate Spacer Induced Stress For Device Enhancement App 20110266628 - HO; Vincent ; et al.	2011-11-03
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS Grant 7,999,325 - Teh , et al. August 16, 2	2011-08-16
Poly profile engineering to modulate spacer induced stress for device enhancement Grant 7,993,997 - Ho , et al. August 9, 2	2011-08-09
Balancing Nfet And Pfet Performance Using Straining Layers App 20110169096 - Chen; Xiangdong ; et al.	2011-07-14
Method and apparatus for post silicide spacer removal Grant 7,977,185 - Greene , et al. July 12, 2	2011-07-12
Method for transistor fabrication with optimized performance Grant 7,883,953 - Zhang , et al. February 8, 2	2011-02-08
Integrated circuit system for suppressing short channel effects Grant 7,867,835 - Lee , et al. January 11, 2	2011-01-11
Dual stress memory technique method and related structure Grant 7,785,950 - Fang , et al. August 31, 2	2010-08-31
Methods of forming semiconductor devices using embedded L-shape spacers Grant 7,759,206 - Luo , et al. July 20, 2	2010-07-20
Method for Transistor Fabrication with Optimized Performance App 20100078687 - Zhang; Da ; et al.	2010-04-01
Spacer-less Low-K Dielectric Processes App 20100059831 - Lee; Yong Meng ; et al.	2010-03-11
Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement App 20090315115 - Zhang; Beichao ; et al.	2009-12-24
Spacer-less low-k dielectric processes Grant 7,615,427 - Lee , et al. November 10, 2	2009-11-10
Integrated Circuit System For Suppressing Short Channel Effects App 20090218636 - Lee; Jae Gon ; et al.	2009-09-03
Method for improved fabrication of a semiconductor using a stress proximity technique process Grant 7,531,401 - Baiocco , et al. May 12, 2	2009-05-12
Poly Profile Engineering To Modulate Spacer Induced Stress For Device Enhancement App 20090085122 - Ho; Vincent ; et al.	2009-04-02
Method To Remove Spacer After Salicidation To Enhance Contact Etch Stop Liner Stress On Mos App 20090026549 - TEH; Young Way ; et al.	2009-01-29
Semiconductor System Having Complementary Strained Channels App 20080315317 - Lai; Chung Woh ; et al.	2008-12-25
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS Grant 7,445,978 - Teh , et al. November 4, 2	2008-11-04
Method For Improved Fabrication Of A Semiconductor Using A Stress Proximity Technique Process App 20080191284 - Baiocco; Christopher Vincent ; et al.	2008-08-14
Integrated Circuit System Having Strained Transistor App 20080142897 - Teh; Young Way ; et al.	2008-06-19
Integrated Circuit System Having Strained Transistor App 20080044967 - Teh; Young Way ; et al.	2008-02-21
Semiconductor Device Having a Dual Stress Liner and Light Exposure Apparatus for Forming the Dual Stress Liner App 20080029823 - Park; Jae-Eon ; et al.	2008-02-07
Differential mechanical stress-producing regions for integrated circuit field effect transistors Grant 7,307,320 - Sun , et al. December 11, 2	2007-12-11
Spacer-less low-k dielectric processes App 20070281410 - Lee; Yong Meng ; et al.	2007-12-06
Methods of fabricating semiconductor devices having a dual stress liner Grant 7,297,584 - Park , et al. November 20, 2	2007-11-20
Spacer And Process To Enhance The Strain In The Channel With Stress Liner App 20070202654 - Ajmera; Atul C. ; et al.	2007-08-30
Composite stress spacer Grant 7,256,084 - Lim , et al. August 14, 2	2007-08-14
Method And Apparatus For Post Silicide Spacer Removal App 20070161244 - Greene; Brian J. ; et al.	2007-07-12
Methods Of Forming Semiconductor Devices Using Embedded L-shape Spacers App 20070122988 - Luo; Zhijiong ; et al.	2007-05-31
Dual Stress Memory Technique Method And Related Structure App 20070105299 - Fang; Sunfei ; et al.	2007-05-10
Differential mechanical stress-producing regions for integrated circuit field effect transistors App 20070102779 - Sun; Min-Chul ; et al.	2007-05-10
Semiconductor device having a dual stress liner, method of manufacturing the semiconductor device and light exposure apparatus for forming the dual stress liner App 20070082439 - Park; Jae-Eon ; et al.	2007-04-12
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS App 20060249794 - Teh; Young Way ; et al.	2006-11-09
Composite stress spacer App 20060252194 - Lim; Khee Yong ; et al.	2006-11-09
Copper metal structure for the reduction of intra-metal capacitance Grant 6,815,823 - Teh , et al. November 9, 2	2004-11-09
Novel copper metal structure for the reduction of intra-metal capacitance App 20040065956 - Teh, Young-Way ; et al.	2004-04-08
Copper metal structure for the reduction of intra-metal capacitance Grant 6,649,517 - Teh , et al. November 18, 2	2003-11-18
Novel copper metal structure for the reduction of intra-metal capacitance App 20020175414 - Teh, Young-Way ; et al.	2002-11-28
Method for fabricating an air gap shallow trench isolation (STI) structure Grant 6,406,975 - Lim , et al. June 18, 2	2002-06-18
Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures Grant 6,380,106 - Lim , et al. April 30, 2	2002-04-30

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