Teehan; Sean

Patent Applications and Registrations

Patent applications and USPTO patent grants for Teehan; Sean.The latest application filed is for "semiconductor device and method of forming the semiconductor device".

Company Profile

11.62.61

Teehan; Sean - Rensselaer NY
Teehan; Sean - Albany NY
Teehan; Sean - Clifton Park NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor Device And Method Of Forming The Semiconductor Device App 20220140074 - Bergendahl; Marc Adam ; et al.	2022-05-05
Semiconductor device and method of forming the semiconductor device Grant 11,239,316 - Bergendahl , et al. February 1, 2	2022-02-01
Semiconductor Device And Method Of Forming The Semiconductor Device App 20210376078 - BERGENDAHL; Marc Adam ; et al.	2021-12-02
Vertical Tunneling Field Effect Transistor With Dual Liner Bottom Spacer App 20210351082 - Miller; Eric ; et al.	2021-11-11
Semiconductor device with reduced contact resistance Grant 11,152,252 - Cheng , et al. October 19, 2	2021-10-19
Vertical tunneling field effect transistor with dual liner bottom spacer Grant 11,152,266 - Miller , et al. October 19, 2	2021-10-19
Nanosheet Channel-to-source And Drain Isolation App 20210305405 - Bergendahl; Marc A. ; et al.	2021-09-30
Semiconductor device and method of forming the semiconductor device Grant 11,127,815 - Bergendahl , et al. September 21, 2	2021-09-21
Transistor gate having tapered segments positioned above the fin channel Grant 11,075,299 - Miller , et al. July 27, 2	2021-07-27
Nanosheet channel-to-source and drain isolation Grant 11,043,581 - Bergendahl , et al. June 22, 2	2021-06-22
Vertical Tunneling Field Effect Transistor With Dual Liner Bottom Spacer App 20210104440 - MILLER; ERIC ; et al.	2021-04-08
Sub-fin removal for SOI like isolation with uniform active fin height Grant 10,937,810 - Bergendahl , et al. March 2, 2	2021-03-02
Transistor Gate Having Tapered Segments Positioned Above The Fin Channel App 20210005749 - Miller; Eric ; et al.	2021-01-07
Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition Grant 10,886,271 - Cheng , et al. January 5, 2	2021-01-05
Super long channel device within VFET architecture Grant 10,833,190 - Bergendahl , et al. November 10, 2	2020-11-10
Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition Grant 10,818,663 - Cheng , et al. October 27, 2	2020-10-27
Nanosheet Channel-to-source And Drain Isolation App 20200266284 - Bergendahl; Marc A. ; et al.	2020-08-20
Air Gap Spacer For Metal Gates App 20200235094 - Bergendahl; Marc A. ; et al.	2020-07-23
Elevator Analytics Facilitating Passenger Destination Prediction And Resource Optimization App 20200130983 - Karve; Gauri ; et al.	2020-04-30
Method and structure for enabling high aspect ratio sacrificial gates Grant 10,629,698 - Cheng , et al.	2020-04-21
Nanosheet channel-to-source and drain isolation Grant 10,615,269 - Bergendahl , et al.	2020-04-07
Air gap spacer for metal gates Grant 10,607,991 - Bergendahl , et al.	2020-03-31
Semiconductor Device With Reduced Contact Resistance App 20200075400 - Cheng; Kangguo ; et al.	2020-03-05
Super long channel device within VFET architecture Grant 10,573,745 - Bergendahl , et al. Feb	2020-02-25
Air gap spacer for metal gates Grant 10,553,581 - Bergendahl , et al. Fe	2020-02-04
Semiconductor device with reduced contact resistance Grant 10,541,172 - Cheng , et al. Ja	2020-01-21
Sub-Fin Removal for SOI Like Isolation with Uniform Active Fin Height App 20190371822 - Bergendahl; Marc A. ; et al.	2019-12-05
Super Long Channel Device Within Vfet Architecture App 20190341490 - Bergendahl; Marc A. ; et al.	2019-11-07
Method and structure for enabling controlled spacer RIE Grant 10,446,452 - Cheng , et al. Oc	2019-10-15
Sub-fin removal for SOI like isolation with uniform active fin height Grant 10,438,972 - Bergendahl , et al. O	2019-10-08
Super long channel device within VFET architecture Grant 10,424,663 - Bergendahl , et al. Sept	2019-09-24
Forming stacked nanowire semiconductor device Grant 10,396,181 - Bergendahl , et al. A	2019-08-27
Semiconductor Device And Method Of Forming The Semiconductor Device App 20190259833 - BERGENDAHL; Marc Adam ; et al.	2019-08-22
Semiconductor Device And Method Of Forming The Semiconductor Device App 20190259832 - BERGENDAHL; Marc Adam ; et al.	2019-08-22
Semiconductor device and method of forming the semiconductor device Grant 10,381,437 - Bergendahl , et al. A	2019-08-13
Margin for fin cut using self-aligned triple patterning Grant 10,304,689 - Karve , et al.	2019-05-28
Vertical transport field effect transistor with precise gate length definition Grant 10,269,931 - Bergendahl , et al.	2019-04-23
Forming stacked nanowire semiconductor device Grant 10,256,326 - Bergendahl , et al.	2019-04-09
Nanosheet channel-to-source and drain isolation Grant 10,249,738 - Bergendahl , et al.	2019-04-02
Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors Grant 10,249,762 - Bergendahl , et al.	2019-04-02
Cyclic etch process to remove dummy gate oxide layer for fin field effect transistor fabrication Grant 10,242,882 - Bi , et al.	2019-03-26
Fin patterns with varying spacing without fin cut Grant 10,217,634 - Bergendahl , et al. Feb	2019-02-26
Fin patterns with varying spacing without fin cut Grant 10,211,055 - Bergendahl , et al. Feb	2019-02-19
Under-channel gate transistors Grant 10,199,503 - Bergendahl , et al. Fe	2019-02-05
Nanosheet Channel-to-source And Drain Isolation App 20180374930 - Bergendahl; Marc A. ; et al.	2018-12-27
Cyclic Etch Process To Remove Dummy Gate Oxide Layer For Fin Field Effect Transistor Fabrication App 20180358232 - Bi; Zhenxing ; et al.	2018-12-13
Fabrication Of Fin Field Effect Transistors For Complementary Metal Oxide Semiconductor Devices Including Separate N-type And P-type Source/drains Using A Single Spacer Deposition App 20180350812 - Cheng; Kangguo ; et al.	2018-12-06
Super Long Channel Device Within Vfet Architecture App 20180342615 - Bergendahl; Marc A. ; et al.	2018-11-29
Super Long Channel Device Within Vfet Architecture App 20180342614 - Bergendahl; Marc A. ; et al.	2018-11-29
Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors Grant 10,141,445 - Bergendahl , et al. Nov	2018-11-27
Method and structure to enable dual channel Fin critical dimension control Grant 10,141,230 - Bergendahl , et al. Nov	2018-11-27
Forming Stacked Nanowire Semiconductor Device App 20180337261 - Bergendahl; Marc A. ; et al.	2018-11-22
Under-channel Gate Transistors App 20180308978 - Bergendahl; Marc A. ; et al.	2018-10-25
Air Gap Spacer For Metal Gates App 20180294263 - Bergendahl; Marc A. ; et al.	2018-10-11
Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition Grant 10,083,962 - Cheng , et al. September 25, 2	2018-09-25
Forming stacked nanowire semiconductor device Grant 10,074,730 - Bergendahl , et al. September 11, 2	2018-09-11
Margin For Fin Cut Using Self-aligned Triple Patterning App 20180226262 - KARVE; Gauri ; et al.	2018-08-09
Air gap spacer for metal gates Grant 10,043,801 - Bergendahl , et al. August 7, 2	2018-08-07
Vertically Aligned Nanowire Channels With Source/drain Interconnects For Nanosheet Transistors App 20180219101 - Bergendahl; Marc A. ; et al.	2018-08-02
Fin patterns with varying spacing without Fin cut Grant 10,026,615 - Bergendahl , et al. July 17, 2	2018-07-17
Fin Patterns With Varying Spacing Without Fin Cut App 20180197739 - Bergendahl; Marc A. ; et al.	2018-07-12
Fin Patterns With Varying Spacing Without Fin Cut App 20180190491 - Bergendahl; Marc A. ; et al.	2018-07-05
Vertical transport field effect transistor with precise gate length definition Grant 10,014,391 - Bergendahl , et al. July 3, 2	2018-07-03
Margin for fin cut using self-aligned triple patterning Grant 9,997,369 - Karve , et al. June 12, 2	2018-06-12
Air Gap Spacer For Metal Gates App 20180158818 - Bergendahl; Marc A. ; et al.	2018-06-07
Fin patterns with varying spacing without fin cut Grant 9,991,117 - Bergendahl , et al. June 5, 2	2018-06-05
Fin patterns with varying spacing without fin cut Grant 9,984,877 - Bergendahl , et al. May 29, 2	2018-05-29
Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors Grant 9,985,138 - Bergendahl , et al. May 29, 2	2018-05-29
Method And Structure For Enabling High Aspect Ratio Sacrificial Gates App 20180122643 - CHENG; Kangguo ; et al.	2018-05-03
Semiconductor Device And Method Of Forming The Semiconductor Device App 20180122947 - Bergendahl; Marc Adam ; et al.	2018-05-03
Electrically conductive interconnect including via having increased contact surface area Grant 9,953,915 - Chen , et al. April 24, 2	2018-04-24
Margin For Fin Cut Using Self-aligned Triple Patterning App 20180090335 - KARVE; Gauri ; et al.	2018-03-29
Nanosheet Channel-to-source And Drain Isolation App 20180083118 - Bergendahl; Marc A. ; et al.	2018-03-22
Sub-Fin Removal for SOI Like Isolation with Uniform Active Fin Height App 20180076225 - Bergendahl; Marc A. ; et al.	2018-03-15
Semiconductor device and method of forming the semiconductor device Grant 9,917,196 - Bergendahl , et al. March 13, 2	2018-03-13
Fabrication Of Fin Field Effect Transistors For Complementary Metal Oxide Semiconductor Devices Including Separate N-type And P-type Source/drains Using A Single Spacer Deposition App 20180069004 - Cheng; Kangguo ; et al.	2018-03-08
Fabrication Of Fin Field Effect Transistors For Complementary Metal Oxide Semiconductor Devices Including Separate N-type And P-type Source/drains Using A Single Spacer Deposition App 20180069003 - Cheng; Kangguo ; et al.	2018-03-08
Vertically Aligned Nanowire Channels With Source/drain Interconnects For Nanosheet Transistors App 20180061946 - BERGENDAHL; Marc A. ; et al.	2018-03-01
Semiconductor Device With Reduced Contact Resistance App 20180061762 - Cheng; Kangguo ; et al.	2018-03-01
Vertically Aligned Nanowire Channels With Source/drain Interconnects For Nanosheet Transistors App 20180061992 - BERGENDAHL; Marc A. ; et al.	2018-03-01
Vertically Aligned Nanowire Channels With Source/drain Interconnects For Nanosheet Transistors App 20180061945 - BERGENDAHL; Marc A. ; et al.	2018-03-01
Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors Grant 9,905,643 - Bergendahl , et al. February 27, 2	2018-02-27
Dummy gate formation using spacer pull down hardmask Grant 9,893,166 - Bergendahl , et al. February 13, 2	2018-02-13
Vertical Transport Field Effect Transistor With Precise Gate Length Definition App 20170373167 - Bergendahl; Marc A. ; et al.	2017-12-28
Vertical Transport Field Effect Transistor With Precise Gate Length Definition App 20170373166 - Bergendahl; Marc A. ; et al.	2017-12-28
Method And Structure To Enable Dual Channel Fin Critical Dimension Control App 20170365525 - Bergendahl; Marc A. ; et al.	2017-12-21
Method and structure for enabling high aspect ratio sacrificial gates Grant 9,842,739 - Cheng , et al. December 12, 2	2017-12-12
Air Gap Spacer For Metal Gates App 20170352657 - Bergendahl; Marc A. ; et al.	2017-12-07
Fin Patterns With Varying Spacing Without Fin Cut App 20170330753 - Bergendahl; Marc A. ; et al.	2017-11-16
Fin Patterns With Varying Spacing Without Fin Cut App 20170330755 - Bergendahl; Marc A. ; et al.	2017-11-16
Fin Patterns With Varying Spacing Without Fin Cut App 20170330754 - Bergendahl; Marc A. ; et al.	2017-11-16
Dummy Gate Formation Using Spacer Pull Down Hardmask App 20170323951 - Bergendahl; Marc A. ; et al.	2017-11-09
Method to form dual channel semiconductor material fins Grant 9,786,666 - Cheng , et al. October 10, 2	2017-10-10
Method and structure to enable dual channel fin critical dimension control Grant 9,768,075 - Bergendahl , et al. September 19, 2	2017-09-19
Single spacer for complementary metal oxide semiconductor process flow Grant 9,754,942 - Bergendahl , et al. September 5, 2	2017-09-05
Single spacer for complementary metal oxide semiconductor process flow Grant 9,748,146 - Bergendahl , et al. August 29, 2	2017-08-29
Single Spacer For Complementary Metal Oxide Semiconductor Process Flow App 20170229350 - BERGENDAHL; MARC A. ; et al.	2017-08-10
Single Spacer For Complementary Metal Oxide Semiconductor Process Flow App 20170229463 - BERGENDAHL; MARC A. ; et al.	2017-08-10
Dummy gate formation using spacer pull down hardmask Grant 9,728,622 - Bergendahl , et al. August 8, 2	2017-08-08
Forming Stacked Nanowire Semiconductor Device App 20170221708 - Bergendahl; Marc A. ; et al.	2017-08-03
Forming Stacked Nanowire Semiconductor Device App 20170222024 - Bergendahl; Marc A. ; et al.	2017-08-03
Method And Structure For Enabling Controlled Spacer Rie App 20170221773 - Cheng; Kangguo ; et al.	2017-08-03
Enabling large feature alignment marks with sidewall image transfer patterning Grant 9,716,184 - Cheng , et al. July 25, 2	2017-07-25
Enabling Large Feature Alignment Marks With Sidewall Image Transfer Patterning App 20170179305 - Cheng; Kangguo ; et al.	2017-06-22
Method and structure for enabling high aspect ratio sacrificial gates Grant 9,659,779 - Cheng , et al. May 23, 2	2017-05-23
Method and structure for enabling controlled spacer RIE Grant 9,627,277 - Cheng , et al. April 18, 2	2017-04-18
Nanosheet channel-to-source and drain isolation Grant 9,620,590 - Bergendahl , et al. April 11, 2	2017-04-11
Air gap spacer for metal gates Grant 9,608,065 - Bergendahl , et al. March 28, 2	2017-03-28
Electrically Conductive Interconnect Including Via Having Increased Contact Surface Area App 20170084534 - Chen; Hsueh-Chung ; et al.	2017-03-23
Electrically conductive interconnect including via having increased contact surface area Grant 9,553,044 - Chen , et al. January 24, 2	2017-01-24
Enabling large feature alignment marks with sidewall image transfer patterning Grant 9,536,744 - Cheng , et al. January 3, 2	2017-01-03
Method To Form Dual Channel Semiconductor Material Fins App 20160372473 - Cheng; Kangguo ; et al.	2016-12-22
Method And Structure For Enabling Controlled Spacer Rie App 20160365292 - Cheng; Kangguo ; et al.	2016-12-15
Single spacer for complementary metal oxide semiconductor process flow Grant 9,450,095 - Bergendahl , et al. September 20, 2	2016-09-20
Method And Structure For Enabling High Aspect Ratio Sacrificial Gates App 20160233095 - CHENG; Kangguo ; et al.	2016-08-11
Method to form dual channel semiconductor material fins Grant 9,362,179 - Cheng , et al. June 7, 2	2016-06-07
Electrically Conductive Interconnect Including Via Having Increased Contact Surface Area App 20160126183 - Chen; Hsueh-Chung ; et al.	2016-05-05
Epitaxially grown quantum well finFETs for enhanced pFET performance Grant 9,331,073 - Bergendahl , et al. May 3, 2	2016-05-03
Method and structure for enabling high aspect ratio sacrificial gates Grant 9,318,574 - Cheng , et al. April 19, 2	2016-04-19
Epitaxially Grown Quantum Well Finfets For Enhanced Pfet Performance App 20160093697 - Bergendahl; Marc A. ; et al.	2016-03-31
Epitaxially Grown Quantum Well Finfets For Enhanced Pfet Performance App 20160093613 - Bergendahl; Marc A. ; et al.	2016-03-31
Method And Structure For Enabling High Aspect Ratio Sacrificial Gates App 20150372113 - CHENG; Kangguo ; et al.	2015-12-24
Method And Structure For Enabling High Aspect Ratio Sacrificial Gates App 20150372127 - CHENG; Kangguo ; et al.	2015-12-24

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