Taylor, Jr.; William J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Taylor, Jr.; William J..The latest application filed is for "electrostatic discharge devices".

Company Profile

1.45.35

Taylor, Jr.; William J. - Clifton Park NY
Taylor, Jr.; William J. - Round Rock TX
Taylor, Jr.; William J. - Austin TX
Taylor, Jr.; William J. - Marietta GA
Taylor, Jr.; William J. - Norcross GA
Taylor, Jr.; William J. - Decatur GA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
True random number generation and physically unclonable functions using voltage control of magnetic anisotropy effects in STT-MRAM Grant 11,435,982 - Dixit , et al. September 6, 2	2022-09-06
Electrostatic Discharge Devices App 20220254773 - LI; Zhiqing ; et al.	2022-08-11
Structure providing charge controlled electronic fuse Grant 11,387,353 - Singh , et al. July 12, 2	2022-07-12
Structure Providing Charge Controlled Electronic Fuse App 20210399116 - Singh; Jagar ; et al.	2021-12-23
True Random Number Generation And Physically Unclonable Functions Using Voltage Control Of Magnetic Anisotropy Effects In Stt-mram App 20210240445 - Dixit; Hemant M. ; et al.	2021-08-05
Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer Grant 9,786,607 - Fan , et al. October 10, 2	2017-10-10
Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer Grant 9,728,456 - Fan , et al. August 8, 2	2017-08-08
Interconnect Structure Including Middle Of Line (mol) Metal Layer Local Interconnect On Etch Stop Layer App 20170140984 - Fan; Su Chen ; et al.	2017-05-18
Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer Grant 9,583,442 - Fan , et al. February 28, 2	2017-02-28
Interconnect Structure Including Middle Of Line (mol) Metal Layer Local Interconnect On Etch Stop Layer App 20170018459 - Fan; Su Chen ; et al.	2017-01-19
Interconnect Structure Including Middle Of Line (mol) Metal Layer Local Interconnect On Etch Stop Layer App 20160379932 - Fan; Su Chen ; et al.	2016-12-29
Methods of increasing silicide to epi contact areas and the resulting devices Grant 9,461,171 - Xie , et al. October 4, 2	2016-10-04
Semiconductor Devices With Conductive Contact Structures Having A Larger Metal Silicide Contact Area App 20160190339 - Xie; Ruilong ; et al.	2016-06-30
Buried fin contact structures on FinFET semiconductor devices Grant 9,362,403 - Xie , et al. June 7, 2	2016-06-07
Methods of forming contact structures for semiconductor devices and the resulting devices Grant 9,330,972 - Xie , et al. May 3, 2	2016-05-03
Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices Grant 9,318,552 - Xie , et al. April 19, 2	2016-04-19
Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material Grant 9,299,781 - Xie , et al. March 29, 2	2016-03-29
Methods Of Forming Contact Structures For Semiconductor Devices And The Resulting Devices App 20160049332 - Xie; Ruilong ; et al.	2016-02-18
Methods for removing selected fins that are formed for finFET semiconductor devices Grant 9,263,340 - Taylor, Jr. , et al. February 16, 2	2016-02-16
Finfet Semiconductor Devices With Stressed Layers App 20160043223 - Xie; Ruilong ; et al.	2016-02-11
Methods of forming spacers on FinFETs and other semiconductor devices Grant 9,231,051 - Cai , et al. January 5, 2	2016-01-05
Forming Gate And Source/drain Contact Openings By Performing A Common Etch Patterning Process App 20150364378 - Xie; Ruilong ; et al.	2015-12-17
Semiconductor Devices With A Layer Of Material Having A Plurality Of Source/drain Trenches App 20150349053 - Xie; Ruilong ; et al.	2015-12-03
Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices Grant 9,202,918 - Xie , et al. December 1, 2	2015-12-01
Methods Of Forming Conductive Contact Structures For A Semiconductor Device With A Larger Metal Silicide Contact Area And The Resulting Devices App 20150340457 - Xie; Ruilong ; et al.	2015-11-26
Methods Of Increasing Silicide To Epi Contact Areas And The Resulting Devices App 20150340497 - Xie; Ruilong ; et al.	2015-11-26
Buried fin contact structures on FinFET semiconductor devices App 20150340452 - Xie; Ruilong ; et al.	2015-11-26
Methods For Removing Selected Fins That Are Formed For Finfet Semiconductor Devices App 20150318215 - Taylor, Jr.; William J. ; et al.	2015-11-05
Methods of forming semiconductor devices using a layer of material having a plurality of trenches formed therein Grant 9,171,934 - Xie , et al. October 27, 2	2015-10-27
Methods of forming contact structures on finfet semiconductor devices and the resulting devices Grant 9,153,694 - Xie , et al. October 6, 2	2015-10-06
Semiconductor Devices With Contact Structures And A Gate Structure Positioned In Trenches Formed In A Layer Of Material App 20150279935 - Xie; Ruilong ; et al.	2015-10-01
Methods Of Forming Semiconductor Devices Using A Layer Of Material Having A Plurality Of Trenches Formed Therein App 20150279972 - Xie; Ruilong ; et al.	2015-10-01
Methods Of Forming A Non-planar Ultra-thin Body Device App 20150255555 - Xie; Ruilong ; et al.	2015-09-10
Methods of forming stressed fin channel structures for FinFET semiconductor devices Grant 9,117,930 - Kamineni , et al. August 25, 2	2015-08-25
Methods Of Forming Spacers On Finfets And Other Semiconductor Devices App 20150145071 - Cai; Xiuyu ; et al.	2015-05-28
Methods Of Forming Stressed Layers On Finfet Semiconductor Devices And The Resulting Devices App 20150076609 - Xie; Ruilong ; et al.	2015-03-19
Methods Of Forming Contact Structures On Finfet Semiconductor Devices And The Resulting Devices App 20150060960 - Xie; Ruilong ; et al.	2015-03-05
Methods of forming spacers on FinFETs and other semiconductor devices Grant 8,962,413 - Cai , et al. February 24, 2	2015-02-24
Methods Of Forming Stressed Fin Channel Structures For Finfet Semiconductor Devices App 20150041906 - Kamineni; Vimal K. ; et al.	2015-02-12
Methods Of Forming Spacers On Finfets And Other Semiconductor Devices App 20150044855 - Cai; Xiuyu ; et al.	2015-02-12
Methods of forming spacers on FinFETs and other semiconductor devices Grant 8,900,941 - Cai , et al. December 2, 2	2014-12-02
Methods of forming stressed fin channel structures for FinFET semiconductor devices Grant 8,889,500 - Kamineni , et al. November 18, 2	2014-11-18
Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device Grant 8,877,588 - Pham , et al. November 4, 2	2014-11-04
Methods Of Repairing Damaged Insulating Materials By Introducing Carbon Into The Layer Of Insulating Material App 20140256064 - Taylor, JR.; William J. ; et al.	2014-09-11
Methods Of Forming A Three-dimensional Semiconductor Device With A Dual Stress Channel And The Resulting Device App 20140225168 - Pham; Daniel T. ; et al.	2014-08-14
Methods of forming a three-dimensional semiconductor device with a nanowire channel structure Grant 8,728,885 - Pham , et al. May 20, 2	2014-05-20
Methods of forming a silicon seed layer and layers of silicon and silicon-containing material therefrom Grant 8,664,093 - Pham , et al. March 4, 2	2014-03-04
Methods Of Forming A Silicon Seed Layer And Layers Of Silicon And Silicon-containing Material Therefrom App 20130309846 - Pham; Daniel T. ; et al.	2013-11-21
Methods Of Forming Spacers On Finfets And Other Semiconductor Devices App 20130292805 - CAI; Xiuyu ; et al.	2013-11-07
Process for making a semiconductor device using partial etching Grant 7,910,442 - Taylor, Jr. , et al. March 22, 2	2011-03-22
Dual gate oxide device integration Grant 7,709,331 - Karve , et al. May 4, 2	2010-05-04
Method for forming a dual metal gate structure Grant 7,666,730 - Karve , et al. February 23, 2	2010-02-23
Method for Implant Imaging with Spin-on Hard Masks App 20090325106 - Conley; Willard E. ; et al.	2009-12-31
Forming a semiconductor device having a metal electrode and structure thereof Grant 7,544,595 - Taylor, Jr. June 9, 2	2009-06-09
Dual Gate Oxide Device Integration App 20090068807 - Karve; Gauri V. ; et al.	2009-03-12
Process For Making A Semiconductor Device Using Partial Etching App 20090029538 - Taylor, JR.; William J. ; et al.	2009-01-29
Method For Forming A Dual Metal Gate Structure App 20090004792 - Karve; Gauri V. ; et al.	2009-01-01
Method for forming a dual metal gate structure Grant 7,445,981 - Karve , et al. November 4, 2	2008-11-04
Semiconductor structure having a metallic buffer layer and method for forming Grant 7,365,410 - Demkov , et al. April 29, 2	2008-04-29
Semiconductor device with low resistance contacts Grant 7,179,700 - Adetutu , et al. February 20, 2	2007-02-20
Method for forming an electronic structure using etch Grant 6,849,487 - Taylor, Jr. , et al. February 1, 2	2005-02-01
Semiconductor process for disposable sidewall spacers Grant 6,849,515 - Taylor, Jr. , et al. February 1, 2	2005-02-01
Method of recrystallizing an amorphous region of a semiconductor Grant 6,573,160 - Taylor, Jr. , et al. June 3, 2	2003-06-03
Transistor having a high K dielectric and short gate length and method therefor Grant 6,514,808 - Samavedam , et al. February 4, 2	2003-02-04
Semiconductor device and method therefor App 20030015758 - Taylor, JR, William J. ; et al.	2003-01-23
Transistor with shaped gate electrode and method therefor Grant 6,475,841 - Taylor, Jr. , et al. November 5, 2	2002-11-05
Semiconductor device and a process for forming the same Grant 6,423,632 - Samavedam , et al. July 23, 2	2002-07-23
Method and apparatus for forming a semiconductor device utilizing a low temperature process App 20020048910 - Taylor, Jr., William J. ; et al.	2002-04-25
Method for forming a semiconductor device Grant 6,362,057 - Taylor, Jr. , et al. March 26, 2	2002-03-26
Method for forming a semiconductor device with an opening in a dielectric layer Grant 6,362,071 - Nguyen , et al. March 26, 2	2002-03-26
Process for fabricating a non-volatile memory cell in a semiconductor device Grant 5,633,186 - Shum , et al. May 27, 1	1997-05-27
Folding knife with moveable pivot axis Grant 5,495,674 - Taylor, Jr. March 5, 1	1996-03-05
Lever-actuated folding knife Grant 5,331,741 - Taylor, Jr. July 26, 1	1994-07-26
Knife opening mechanism Grant 4,719,700 - Taylor, Jr. January 19, 1	1988-01-19
Drum magazine for carbines or the like Grant 4,413,546 - Taylor, Jr. November 8, 1	1983-11-08
Drum magazine for automatic pistol or the like Grant 4,332,097 - Taylor, Jr. June 1, 1	1982-06-01

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