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Patent applications and USPTO patent grants for Tavares; Andrea Iabrudi.The latest application filed is for "systems and methods for automatic formal metastability fault analysis in an electronic design".
Patent | Date |
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Systems and methods for automatic formal metastability fault analysis in an electronic design Grant 10,769,008 - Arias Drake , et al. Sep | 2020-09-08 |
Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques Grant 10,204,201 - Loh , et al. Feb | 2019-02-12 |
Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design Grant 10,094,875 - Lin , et al. October 9, 2 | 2018-10-09 |
Method, system, and computer program product for verifying an electronic circuit design with a graph-based proof flow Grant 9,817,930 - Campos , et al. November 14, 2 | 2017-11-14 |
Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths Grant 9,633,151 - Sun , et al. April 25, 2 | 2017-04-25 |
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