Taur; Yuan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Taur; Yuan.The latest application filed is for "self-aligned double-gate mosfet by selective epitaxy and silicon wafer bonding techniques".

Company Profile

0.13.1

Taur; Yuan - Bedford NY
Taur; Yuan - Armonk NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques Grant 6,759,710 - Chan , et al. July 6, 2	2004-07-06
Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques App 20020093053 - Chan, Kevin K. ; et al.	2002-07-18
Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques Grant 6,365,465 - Chan , et al. April 2, 2	2002-04-02
Forming steep lateral doping distribution at source/drain junctions Grant 6,268,640 - Park , et al. July 31, 2	2001-07-31
Field effect transistors with improved implants and method for making such transistors Grant 6,143,635 - Boyd , et al. November 7, 2	2000-11-07
Method for making field effect transistors having sub-lithographic gates with vertical side walls Grant 6,040,214 - Boyd , et al. March 21, 2	2000-03-21
Vertical double-gate field effect transistor Grant 5,780,327 - Chu , et al. July 14, 1	1998-07-14
SOI CMOS structure Grant 5,767,549 - Chen , et al. June 16, 1	1998-06-16
Vertical double-gate field effect transistor Grant 5,689,127 - Chu , et al. November 18, 1	1997-11-18
Method for fabricating a self-aligned double-gate MOSFET by selective lateral epitaxy Grant 5,646,058 - Taur , et al. July 8, 1	1997-07-08
Self-aligned double-gate MOSFET by selective lateral epitaxy Grant 5,604,368 - Taur , et al. February 18, 1	1997-02-18
SOI lateral bipolar transistor with edge-strapped base contact and method of fabricating same Grant 5,298,786 - Shahidi , et al. March 29, 1	1994-03-29
System for real-time monitoring the characteristics, variations and alignment errors of lithography structures Grant 4,585,342 - Lin , et al. April 29, 1	1986-04-29
Single mask process for fabricating CMOS structure Grant 4,509,991 - Taur April 9, 1	1985-04-09

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.